Cross-point memory and methods for fabrication of same

US10367033B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10367033-B2
Application numberUS-201816112570-A
CountryUS
Kind codeB2
Filing dateAug 24, 2018
Priority dateNov 21, 2013
Publication dateJul 30, 2019
Grant dateJul 30, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction.

First claim

Opening claim text (preview).

What is claimed is: 1. A method, comprising: forming a first conductive line and a second conductive line extending in a first direction, the first conductive line and the second conductive line separated by a space; covering, with a liner material, sidewalls of the first conductive line and the second conductive line and a surface extending between the sidewalls; depositing a dielectric material over the liner material, wherein a first sidewall and a second sidewall of the dielectric material are in contact with the liner material; and forming a pillar of a memory cell stack on the first conductive line or the second conductive line after depositing the dielectric material. 2. The method of claim 1 , further comprising: depositing a pillar liner in contact with a plurality of side surfaces of the pillar, wherein the pillar liner is in contact with the dielectric material and the liner material. 3. The method of claim 2 , further comprising: depositing a pillar insulating material in contact with the pillar liner, wherein the pillar insulating material is different than the pillar liner. 4. The method of claim 1 , further comprising: patterning a third conductive line over the pillar, the third conductive line extending in a second direction that intersects the first direction.

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What does patent US10367033B2 cover?
A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack compris…
Who is the assignee on this patent?
Micron Technology Inc
What technology area does this patent fall under?
Primary CPC classification H01L27/2463. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 30 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).