Location-specific laser annealing to improve interconnect microstructure

Patent metadata

Field	Value
Publication number	US-10366920-B2
Application number	US-201615198450-A
Country	US
Kind code	B2
Filing date	Jun 30, 2016
Priority date	Jun 30, 2016
Publication date	Jul 30, 2019
Grant date	Jul 30, 2019

Abstract

A method (and structure) includes performing an initial partial anneal of a metal interconnect overburden layer for semiconductor devices being fabricated on a chip on a semiconductor wafer. Orientation of an early recrystallizing grain at a specific location on a top surface of the metal overburden layer is determined, as implemented and controlled by a processor on a computer. A determination is made whether the orientation of the early recrystallizing grain is desirable or undesirable.

First claim

What is claimed is:

1. A method, comprising: performing an initial partial anneal of a metal interconnect and overburden layer for semiconductor devices being fabricated on a chip on a semiconductor wafer; receiving image data of a top surface of the metal interconnect and overburden layer as image data from a scanning electron microscope (SEM) equipped with electron backscatter diffraction (EBSD); detecting an orientation of an early recrystallizing grain at a specific location on the top surface of the metal overburden layer, as implemented and controlled by a processor on a computer, in a process of selectively stepping through the image data at a preset sampling interval predetermined as based on an expected overburden grain size; determining whether the detected orientation of the early recrystallizing grain is desirable or undesirable; and selectively performing a laser anneal at specific locations to at least one of promote or inhibit certain grain orientations from growing, as based on the determining of being desirable or undesirable.

2. The method of claim 1 , wherein said metal overburden layer comprises copper (Cu).

3. The method of claim 1 , wherein said specific location comprises a point of a plurality of points of a discrete sampling grid of said top surface, said discrete sampling grid having a sample interval based on an expected overburden grain size.

4. The method of claim 3 , wherein said discrete sampling grid is selectively applied to at least one of different regions and different layers of a chip during fabrication of a semiconductor wafer.

5. The method of claim 1 , further comprising:
monitoring said initial partial anneal by using a laser interferometer to measure a flexure of said wafer; and
determining, from measurements of said wafer flexure, when to terminate said initial partial anneal in order to implement said detecting and determining of early grain recrystallization orientation.

6. The method of method 1 , further comprising highlighting an area around an early recrystallizing grain that is determined as having a grain orientation that is of interest.

7. The method of claim 1 , further comprising determining a raster pattern for a subsequent laser anneal that will complete an annealing of said metal interconnect overburden layer, based on said determining whether said orientation of said grain is desirable or is undesirable.

8. The method of claim 7 , further comprising using said processor to control one or more of a focus, an energy level, and a projection location on said wafer of a laser beam, to follow said determined raster pattern.

9. The method of claim 8 , wherein said raster pattern comprises one or more of:
an inclusion mode pattern of straight lines over a specific grain to impart heat energy to encourage crystallization at said specific grain;
an exclusion mode pattern avoiding a specific grain having an undesirable orientation while providing energy to promote other orientations on a remainder of a sample around an exclusion radius of said specific grain; and
a mixed pattern in which grains with undesired orientations are avoided, grains with desired orientations are promoted, and regions not near desired grains receive a background fluence level.

10. A method of annealing a metal interconnect overburden layer, said method comprising: performing an initial partial anneal of said metal interconnect overburden layer for semiconductor devices being fabricated on a chip on a semiconductor wafer; determining an orientation of early recrystallizing grains at specific locations on a top surface of the metal overburden layer, as implemented and controlled by a processor on a computer; determining whether said orientations of the early recrystallizing grains at said specific locations is desirable or undesirable; selectively performing a laser anneal of said metal interconnect overburden layer, as implemented and controlled by said processor on said computer, in a manner that selectively promotes or inhibits grain orientations from growing at selective locations on said metal interconnect overburden layer; and determining points of a discrete sampling grid of said top surface, said discrete sampling grid having a sample interval based on an expected overburden grain size, said determined discrete sampling grid points comprising said specific locations on said top surface being sampled for said determining of grain orientation.

11. The method of claim 10 , further comprising further comprising:
monitoring said initial partial anneal by using a laser interferometer to measure a flexure of said wafer; and
determining, from measurements of said wafer flexure, when to remove said wafer from said initial partial anneal for said determining of early grain recrystallization orientation.

12. The method of claim 10 , wherein said determining of orientation comprises evaluation of grain orientation using a scanning electron microscope (SEM) equipped with electron backscatter diffraction (EBSD).

Assignees

• IBM

Inventors

• Briggs Benjamin David
• Clevenger Lawrence A
• Deprospo Bartlet H
• Rizzolo Michael

Classifications

• H10P74/238 Primary

  comprising acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection or in-situ thickness measurement · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P72/0436

  mainly by radiation · CPC title

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title