Fully aligned via in ground rule region

Patent metadata

Field	Value
Publication number	US-10366919-B2
Application number	US-201715709956-A
Country	US
Kind code	B2
Filing date	Sep 20, 2017
Priority date	Sep 20, 2017
Publication date	Jul 30, 2019
Grant date	Jul 30, 2019

Abstract

The present disclosure relates to semiconductor structures and, more particularly, to fully aligned via structures and methods of manufacture. The structure includes: a plurality of minimum ground rule conductive structures formed in a dielectric material each of which comprises a recessed conductive material therein; at least one conductive structure formed in the dielectric material which is wider than the plurality of minimum ground rule conductive structures; an etch stop layer over a surface of the dielectric layer with openings to expose the conductive material of the least one conductive structure and the recessed conductive material of a selected minimum ground rule conductive structure; and an upper conductive material fully aligned with and in direct electrical contact with the at least one conductive structure and the selected minimum ground rule conductive structure, through the openings of the etch stop layer.

First claim

What is claimed:

1. A structure comprising:
a plurality of minimum ground rule conductive structures formed in a dielectric material each of which comprises a recessed conductive material therein;
at least one conductive structure formed in the dielectric material which is wider than the plurality of minimum ground rule conductive structures;
an etch stop layer over a surface of the dielectric layer with openings to expose the conductive material of the least one conductive structure and the recessed conductive material of a selected minimum ground rule conductive structure; and
an upper conductive material fully aligned with and in direct electrical contact with the at least one conductive structure and the selected minimum ground rule conductive structure, through the openings of the etch stop layer,
wherein the etch stop layer is directly on the recessed conductive material of another selected minimum ground rule conductive structure and the opening exposes the recessed conductive material of the selected minimum ground rule conductive structure and partly exposes an upper surface of the conductive material of the least one conductive structure.

2. The structure of claim 1 , wherein the recessed conductive material is Ru.

3. The structure of claim 1 , wherein the recessed conductive material is Co.

4. The structure of claim 1 , wherein conductive material of at least one conductive structure is planar with the dielectric material.

5. The structure of claim 4 , wherein a recessed liner is under the conductive material.

6. The structure of claim 5 , wherein the recessed liner is a same material as the recessed conductive material.

7. The structure of claim 6 , wherein the upper conductive material is in electrical contact with the recessed liner and the conductive material.

8. The structure of claim 7 , wherein the conductive material of the at least one conductive structure is planar with the dielectric material.

9. A structure comprising:
a plurality of minimum ground rule structures each of which comprises a recessed conductive material and having a minimum insulator spacing therebetween;
at least one wiring structure having a larger dimension than the plurality of minimum ground rule structures, the at least one wiring structure comprising a liner material and a conductive material which is different than the recessed conductive material; and
an upper interconnect structure fully aligned with and in direct electrical contact with a selected minimum ground rule structure and the at least one wiring structure.

10. The structure of claim 9 , wherein the recessed conductive material is Ru.

11. The structure of claim 9 , wherein the recessed conductive material is Co.

12. The structure of claim 9 , wherein conductive material of the at least one wiring structure is planar with a dielectric material which is for a same wiring level as the plurality of minimum ground rule structures.

13. The structure of claim 9 , wherein a recessed liner is under a primary conductive material of the at least one wiring structure.

14. The structure of claim 13 , wherein the recessed liner is a same material as the recessed conductive material.

15. The structure of claim 14 , wherein the upper interconnect structure is in electrical contact with the recessed liner and surrounds the conductive material.

16. The structure of claim 14 , wherein the primary conductive material is planar with a dielectric material of a same wiring layer of the plurality of minimum ground rule structures.

17. The structure of claim 1 , further comprising a single liner under and in direct contact with the recessed conductive material of the plurality of the minimum ground rule conductive structures, and a barrier layer and a liner are directly under the conductive material of the least one conductive structure.

18. The structure of claim 9 , further comprising:
an etch stop layer with openings to expose an upper surface of a first of the recessed conductive material having the minimum insulator spacing, and covering a second of the recessed conductive material having the minimum insulator spacing;
the at least one wiring structure further comprising a second conductor material over the conductive material, with the conductive material being recessed; and
the upper interconnect structure is in directed electrical contact the recessed conductive material and the second conductive material.

Assignees

• Globalfoundries Inc

Inventors

• Licausi Nicholas V
• Zhang Xunyuan

Classifications

• H10P50/667

  by liquid etching only · CPC title

• H10P50/266

  by vapour etching only · CPC title

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title