Systems and methods for testing a semiconductor memory device having a reference memory array

Patent metadata

Field	Value
Publication number	US-10366772-B2
Application number	US-201715684756-A
Country	US
Kind code	B2
Filing date	Aug 23, 2017
Priority date	Apr 15, 2016
Publication date	Jul 30, 2019
Grant date	Jul 30, 2019

Abstract

Semiconductor memory testing devices and methods are disclosed. In one respect, a device is disclosed that includes a first memory cell array having a first bit-line and a plurality of first memory cells coupled to the first bit-line; a second memory cell array having a second bit-line and a plurality of second memory cells coupled to the second bit-line, the number of second memory cells being smaller than that of the first memory cells; a sense amplifier coupled to the first bit-line and a first end of the second bit-line; a word decoder configured to operate the second memory cells responsive to a first test signal; and a transistor coupled to a second end of the second bit-line and operated by a second test signal.

First claim

The invention claimed is:

1. An apparatus comprising:
a first memory cell array comprising a first bit-line and a plurality of normal word lines coupled to the first bit-line;
a second memory cell array comprising a second bit-line and a plurality of dummy word lines coupled to the second hit-line, the number of dummy word lines being smaller than that of the normal word lines;
a sense amplifier coupled to the first bit-line and a first end of the second bit-line;
a first word decoder configured to activate one of the plurality of normal word lines during a memory access operation to a memory cell coupled to the one of the plurality of normal word lines;
a second word decoder configured to activate two or more of the plurality of dummy word lines during the memory access operation and further configured to operate selected ones of the plurality of dummy word lines responsive to a first test signal; and
a transistor coupled to a second end of the second bit-line and operated by a second test signal.

2. The apparatus of claim 1 , further comprising:
a transistor edge network including a plurality of bit-line transistors each coupled to bit-lines in the second memory cell array;
wherein the transistor is coupled to the second end of the second bit-line through the transistor edge network.

3. The apparatus of claim 2 , wherein the transistor edge network receives a merged bit-line output from each bit-line in the second memory cell array and joins the merged bit-line outputs together into a bundled output that is provided to the transistor.

4. The apparatus of claim 3 , wherein the second test signal additionally operates to turn off a power supply in the sense amplifier which generates the merged bit-line outputs by enabling voltage sharing between the bit-lines of the first and second memory cell arrays.

5. The apparatus of claim 3 , further comprising:
a comparator having a first input coupled to the transistor and a second input coupled to a reference voltage; wherein
the comparator is configured to compare the bundled output provided by the transistor to the reference voltage and to provide a responsive output signal at a comparator output.

6. The apparatus of claim 5 , wherein
the responsive output signal includes one of two possible output states such that the particular output state provided by the comparator output at a particular time depends on a comparison of the first and second comparator inputs; and
a transition between output states indicates that capacitance on the first and second bit-lines is substantially balanced.

7. The apparatus of claim 5 , wherein
the comparator output is used in a test mode that is executed to determine the activated two or more of the plurality of dummy word line for the second memory cell array.

8. The apparatus of claim 1 , wherein the second memory cell array is a reference array arranged at an edge of the apparatus.

9. The apparatus of claim 1 , wherein the second memory cell array is a reference array arranged between memory banks associated with the apparatus.

10. An apparatus comprising:
a normal memory cell array comprising a first bit-line and a plurality of normal word lines coupled to the first bit-line;
a reference memory cell array comprising a second bit-line and a plurality of dummy word lines coupled to the second bit-line, the number of dummy word lines being smaller than that of the normal word lines and arranged at an edge of the apparatus;
a sense amplifier coupled to the first bit-line and a first end of the second bit-line;
a first word decoder configured to activate one of the plurality of normal word lines during a memory access operation to a memory cell coupled to the one of the plurality of normal word lines;
a second word decoder configured to activate two or more of the plurality of dummy word lines during the memory access operation and further configured to operate selected ones of the plurality of dummy word lines responsive to a first test signal; and
a transistor coupled to a second end of the second bit-line and operated by a second test signal,
wherein the sense amplifier senses information on the first and second bit lines responsive to the one of the plurality of normal word lines and the two or more of the plurality of dummy word lines being activated.

11. The apparatus of claim 10 , further comprising:
a transistor edge network including a plurality of bit-line transistors each coupled to bit-lines in the second memory cell array;
wherein the transistor is coupled to the second end of the second bit-line through the transistor edge network.

12. The apparatus of claim 11 , wherein the transistor edge network receives a merged bit-line output from each bit-line in the reference memory cell array and joins the merged bit-line outputs together into a bundled output that is provided to the transistor.

13. The apparatus of claim 12 , wherein the second test signal additionally operates to turn off a power supply in the sense amplifier which generates the merged bit-line outputs by enabling voltage sharing between the bit-lines of the normal and reference memory cell arrays.

14. The apparatus of claim 12 , further comprising:
a comparator having a first input coupled to the transistor and a second input coupled to a reference voltage; wherein
the comparator is configured to compare the bundled output provided by the transistor to the reference voltage and to provide a responsive output signal at a comparator output.

15. The apparatus of claim 14 , wherein
the responsive output signal includes one of two possible output states such that the particular output state provided by the comparator output at a particular time depends on a comparison of the first and second comparator inputs; and
a transition between output states indicates that capacitance on the first and second bit-lines is substantially balanced.

16. The apparatus of claim 14 , wherein
the comparator output is used in a test mode that is executed to determine the activated two or more of the plurality of dummy word line for the reference memory cell array.

Assignees

• Micron Technology Inc

Inventors

• He Yuan
• Ito Yutaka

Classifications

• G11C29/24

  Accessing extra cells, e.g. dummy cells or redundant cells · CPC title

• G11C11/401

  forming cells needing refreshing or charge regeneration, i.e. dynamic cells · CPC title

• G11C29/18

  Address generation devices; Devices for accessing memories, e.g. details of addressing circuits · CPC title

• G11C29/12005

  comprising voltage or current generators · CPC title

• G11C2029/1802

  Address decoder · CPC title