Systems and methods for testing a semiconductor memory device having a reference memory array

Patent metadata

Field	Value
Publication number	US-9767919-B1
Application number	US-201615130789-A
Country	US
Kind code	B1
Filing date	Apr 15, 2016
Priority date	Apr 15, 2016
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

Semiconductor memory testing devices and methods are disclosed. In one respect, a device is disclosed that includes a first memory cell array having a first bit-line and a plurality of first memory cells connected to the first bit-line; a second memory cell array having a second bit-line and a plurality of second memory cells connected to the second bit-line, the number of second memory cells being smaller than that of the first memory cells; a sense amplifier connected to the first bit-line and a first end of the second bit-line; a word decoder configured to operate the second memory cells responsive to a first test signal; and a transistor coupled to a second end of the second bit-line and operated by a second test signal.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a first memory cell array comprising a first bit-line and a plurality of first memory cells connected to the first bit-line;
a second memory cell array comprising a second bit-line and a plurality of second memory cells connected to the second bit-line, the number of second memory cells being smaller than that of the first memory cells;
a sense amplifier connected to the first bit-line and a first end of the second bit-line;
a word decoder configured to operate the second memory cells responsive to a first test signal;
a transistor coupled to a second end of the second bit-line and operated by a second test signal; and
a transistor edge network including a plurality of bit-line transistors each coupled to bit-lines in the second memory cell array, wherein the transistor is coupled to the second end of the second bit-line through at least one bit-line transistor of the transistor edge network.

2. The semiconductor device of claim 1 , wherein the transistor edge network receives a merged bit-line output from each bit-line in the second memory cell array and joins the merged bit-line outputs together into a bundled output that is provided to the transistor.

3. The semiconductor device of claim 2 , wherein the second test signal additionally operates to turns off a power supply in the sense amplifier which generates the merged bit-line outputs by enabling voltage sharing between the bit-lines of the first and second memory cell arrays.

4. The semiconductor device of claim 2 , further comprising:
a comparator having a first input coupled to the output transistor and a second input coupled to a reference voltage; wherein
the comparator is configured to compare the bundled output provided by the transistor to the reference voltage and to provide a responsive output signal at a comparator output.

5. The semiconductor device of claim 4 , wherein
the responsive output signal includes one of two possible output states such that the particular output state provided by the comparator output at a particular time depends on a comparison of the first and second comparator inputs; and
a transition between output states indicates that capacitance on the first and second bit-lines is substantially balanced.

6. The semiconductor device of claim 4 , wherein
the comparator output is used in a test mode that is executed to determine an activated word-line group for the second memory cell array; and
the activated word-line group including at least some of a plurality of word-lines in the second memory cell array to be activated to support a balanced operation of the sense amplifier during a normal operation mode.

7. The semiconductor device of claim 6 , wherein the test mode comprises:
a first phase in which the comparator output is monitored to determine the activated word-line group based on a number of word-lines needed to provide a balanced operation of the sense amplifier; and
a second phase in which defective word-lines in the activated word-line group are found and replaced with dummy word-lines.

8. The semiconductor device of claim 7 , wherein the defective word-lines are determined through a variable voltage that is provided to the second memory array through the transistor edge network.

9. The semiconductor device of claim 6 , wherein, in the normal operation mode, the second memory cell array couples the second memory cells in the activated word-line group to the second bit-line so as to balance a capacitance on the first bit-line during a memory access operation of at least one of the first memory cells.

10. The semiconductor device of claim 9 , further comprising:
at least one dummy word-lines in the first memory cell array that is asserted during a pre-charge phase to balance the capacitance of the memory cells of the activated word-line group.

11. The semiconductor device of claim 1 , the second memory cell array is a reference array arranged at an edge of the semiconductor device.

12. The semiconductor device of claim 1 , the second memory cell array is a reference array arranged between memory banks associated with the semiconductor device.

13. A semiconductor device comprising:
a first memory cell array comprising a first bit-line and a plurality of first memory cells connected to the first bit-line;
a second memory cell array comprising a second bit-line and a plurality of second memory cells connected to the second bit-line, the number of second memory cells being smaller than that of the first memory cells;
a sense amplifier connected to the first bit-line and a first end of the second bit-line;
a word decoder configured to operate the second memory cells responsive to a first test signal;
first and second transistors operated by the first test signal to provide a test output signal through a normal read out pathway;
a first multiplexer having a first input configured to receive a bundled output signal from the first and second transistors and having a second input coupled to a first global bit-line; and
a second multiplexer having a first input coupled to a reference voltage and a second input coupled to a second global bit-line; and
a global sense amplifier connected to outputs of the first and second multiplexers,
wherein in a normal operation mode, the first and second multiplexers provide the first and second global bit-lines to the global sense amplifier as part of a memory access operation, and
wherein in a test mode, the first multiplexer provides the bundled output signal and the second multiplexer provides the reference voltage to the global sense amplifier.

14. The semiconductor device of claim 13 , wherein
in a test mode, global sense amplifier compares the bundled output signal to the reference voltage provides a responsive output signal at a global sense amplifier output; and
responsive output signal is used to determine an activated word-line group for the second memory cell array, the activated word-line group including at least some of a plurality of word-lines in the second memory cell array to be activated to support a balanced operation of the sense amplifier during a normal operation mode.

Assignees

• Micron Technology Inc

Inventors

• He Yuan
• Ito Yutaka

Classifications

• G11C29/18

  Address generation devices; Devices for accessing memories, e.g. details of addressing circuits · CPC title

• G11C11/401

  forming cells needing refreshing or charge regeneration, i.e. dynamic cells · CPC title

• G11C29/24

  Accessing extra cells, e.g. dummy cells or redundant cells · CPC title

• G11C29/38 Primary

  Response verification devices · CPC title

• G11C29/12005

  comprising voltage or current generators · CPC title