Flash controller to provide a value that represents a parameter to a flash memory

Patent metadata

Field	Value
Publication number	US-10366045-B2
Application number	US-201715813963-A
Country	US
Kind code	B2
Filing date	Nov 15, 2017
Priority date	Oct 19, 1999
Publication date	Jul 30, 2019
Grant date	Jul 30, 2019

Abstract

An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting.

First claim

What is claimed is:

1. A method of operation in a memory controller to control a flash memory device having a plurality of control registers to store values, wherein the values represent interface parameter settings for a transceiver of the flash memory device, the method comprising:
receiving parameter information pertaining to the flash memory; and,
transmitting to the flash memory device, control values for storage in the plurality of control registers, the control values being selected based on the received parameter information pertaining to the flash memory device.

2. The method of claim 1 , further comprising deriving the plurality of control values from the parameter information based on a topography of devices coupled to the memory controller, the devices including at least the flash memory device.

3. The method of claim 2 , wherein deriving the plurality of control values from the parameter information based on a topography of devices comprises selecting the control values from a look-up table based on the parameter information.

4. The method of claim 1 , wherein receiving the parameter information comprises receiving the parameter information from a supplemental memory device disposed on a module that includes the flash memory device.

5. The method of claim 1 , wherein the control values include control values to program a drive strength value for a transmitter of the flash memory device.

6. The method of claim 1 , wherein the control values include control values to program a receiver reference voltage for a receiver circuit on the flash memory device.

7. The method of claim 1 , wherein the control values include control values to program one or more of:
a slew rate value for a transmitter of the flash memory device;
an equalization control value for the transmitter of the flash memory device;
a symmetry control parameter for the transmitter of the flash memory device;
a transmit phase offset for the transmitter of the flash memory device; and,
a receive phase offset for a receiver of the flash memory device.

8. The method of claim 1 , wherein the flash memory device is a first flash memory device further comprising transmitting a first device identification (ID) value to the first flash memory device; sending a command to the first flash memory device to propagate the first ID value to a second flash memory device.

9. The method of claim 8 , further comprising transmitting a second device identification (ID) value to the first flash memory device wherein the first ID value uniquely identifies the second flash memory device and the second ID value uniquely identifies the first flash memory device.

10. A memory controller to control a flash memory device having a plurality of control registers to store control values, wherein the control values represent interface parameter settings for a transceiver of the flash memory device, the memory controller comprising:
a circuit to select control values based on received parameter information pertaining to the flash memory; and,
a circuit to transmit to the flash memory device, control values for storage in the plurality of control registers.

11. The memory controller claim 10 , wherein the plurality of control values are derived from the parameter information based on a topography of devices coupled to the memory controller, the devices including at least the flash memory device.

12. The memory controller of claim 11 , wherein the circuit to derive the control values comprises a look-up table, wherein the plurality of control values are selected by the look-up table using the parameter information.

13. The memory controller of claim 10 , wherein the parameter information is received from a supplemental memory device disposed on a module that includes the flash memory device.

14. The memory controller of claim 10 , wherein the control values include control values to program a drive strength value for a transmitter of the flash memory device.

15. The memory controller of claim 10 , wherein the control values include control values to program a receiver reference voltage for a receiver circuit on the flash memory device.

16. The memory controller of claim 10 , wherein the control values include control values to program one or more of:
a slew rate value for a transmitter of the flash memory device;
an equalization control value for the transmitter of the flash memory device;
a symmetry control parameter for the transmitter of the flash memory device;
a transmit phase offset for the transmitter of the flash memory device; and,
a receive phase offset for a receiver of the flash memory device.

17. The memory controller of claim 10 , further comprising:
a first register to store a slew rate value for a transmitter of the memory controller;
a second register to store an equalization control value for the transmitter of the memory controller;
a third register to store a symmetry control parameter for the transmitter of the memory controller;
a fourth register to store a transmit phase offset for the transmitter of the memory controller; and
a fifth register to store a receive phase offset for a receiver of the memory controller.

18. The memory controller of claim 10 , further comprising a register to program a drive strength value for a transmitter of the memory controller.

19. The memory controller of claim 10 , further comprising a register to program a receiver reference voltage for a receiver circuit on the memory controller.

20. A memory controller to control a flash memory device having a plurality of control registers to store values, wherein the values represent interface parameter settings for a transceiver of the flash memory device, the memory controller comprising:
a circuit to derive control values based on received parameter information pertaining to the flash memory; and
a circuit to transmit to the flash memory device, control values for storage in the plurality of control registers, the control values including:
a first control value to program a receiver reference voltage for a receiver circuit on the flash memory device; and
a second control value to program a drive strength value for a transmitter of the flash memory device.

Assignees

• Rambus Inc

Inventors

• Horowitz Mark A
• Hampel Craig E
• Moncayo Alfredo
• Donnelly Kevin S
• Zerbe Jared L

Classifications

• H03K19/018585

  programmable · CPC title

• G11C19/00

  Digital stores in which the information is moved stepwise, e.g. shift registers · CPC title

• G06F13/4243

  with synchronous protocol · CPC title

• G06F13/4086

  Bus impedance matching, e.g. termination · CPC title

• G06F13/1689

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title