Flash controller to provide a value that represents a parameter to a flash memory

Patent metadata

Field	Value
Publication number	US-9411767-B2
Application number	US-201514875433-A
Country	US
Kind code	B2
Filing date	Oct 5, 2015
Priority date	Oct 19, 1999
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting.

First claim

What is claimed is:

1. A memory controller to control a flash memory, comprising:
a first interface to receive a clock signal from at least one flash memory device; and,
a second interface to couple to the at least one flash memory device, the second interface comprising:
a transmitter circuit to provide, to the at least one flash memory device, a first value representative of a drive strength setting of an output driver to transmit data; and
a receiver circuit to receive the data, synchronously with respect to the clock signal, from the flash memory device.

2. The memory controller to control a flash memory of claim 1 , wherein the first value is derived according to a count of memory devices coupled to the second interface.

3. The memory controller to control a flash memory of claim 1 , wherein the drive strength setting of the output driver is selectable from at least three different values.

4. The memory controller to control a flash memory of claim 1 , wherein the second interface receives parameter information pertaining to the flash memory device and selects the drive strength setting based on the parameter information.

5. The memory controller to control a flash memory of claim 4 , wherein the drive strength setting is selected based on the parameter information received from a serial presence detect memory device.

6. The memory controller to control a flash memory of claim 4 , wherein the second interface derives a second value representative of at least one transmission parameter from the parameter information, the second value being transmitted to the first flash memory device via the second interface.

7. The memory controller to control a flash memory of claim 6 , wherein the second value is derived from the parameter information based on a topology of memory devices coupled to the second interface.

8. A method of operating a memory controller to control a flash memory, comprising:
transmitting, to a bidirectional bus coupled to a flash memory device, a first value representative of a drive strength setting of an output driver of the flash memory device, the first value to be stored in a first register of the flash memory device; and
receiving data from the bidirectional bus synchronously with respect to a clock signal, the data being output by the output driver using the drive strength setting.

9. The method of claim 8 , wherein the first value is derived from a count of memory devices on the bidirectional bus.

10. The method of claim 8 , wherein the drive strength setting of the output driver is selectable from at least three different values.

11. The method of claim 8 , further comprising:
receiving parameter information pertaining to the flash memory device; and,
based on the parameter information, selecting the drive strength setting.

12. The method of claim 11 , wherein the parameter information is received from a serial presence detect memory device.

13. The method of claim 11 , further comprising:
deriving a second value representative of at least one transmission parameter from the parameter information; and,
transmitting, to the bidirectional bus, the second value.

14. The method of claim 13 , wherein the second value is derived from the parameter information based on a topology of memory devices coupled to the bidirectional bus.

15. A memory controller to control a flash memory, comprising:
means for receiving data synchronously with respect to a clock signal from a bidirectional bus; and
means for transmitting, to a flash memory device, a first value representative of a drive strength setting for driving of the data by an output driver of the flash memory device, the first value to be received, by the flash memory device, from the bidirectional bus.

16. The memory controller to control a flash memory of claim 15 , wherein the drive strength setting is derived based on a count of memory devices on the bidirectional bus.

17. The memory controller to control a flash memory of claim 16 , wherein the selected drive strength is selectable from at least three different values.

18. The memory controller to control a flash memory of claim 15 , further comprising:
means for receiving parameter information pertaining to the flash memory device; and,
means for, based on the parameter information, selecting the drive strength setting.

19. The memory controller to control a flash memory of claim 18 , further comprising:
means for controlling a serial presence detect memory device to provide the parameter information.

20. The memory controller to control a flash memory 18 , further comprising:
means for deriving, from the parameter information, a second value representative of at least one transmission parameter, the means for transmitting to provide, to the flash memory device, the second value.

Assignees

• Rambus Inc

Inventors

• Horowitz Mark A
• Hampel Craig E
• Moncayo Alfredo
• Donnelly Kevin S
• Zerbe Jared L

Classifications

• G06F13/4243 Primary

  with synchronous protocol · CPC title

• G06F13/4234

  being a memory bus · CPC title

• G11C19/00

  Digital stores in which the information is moved stepwise, e.g. shift registers · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G11C16/32

  Timing circuits · CPC title