Electronic device for changing clock

Patent metadata

Field	Value
Publication number	US-10365875-B2
Application number	US-201816100021-A
Country	US
Kind code	B2
Filing date	Aug 9, 2018
Priority date	Aug 9, 2017
Publication date	Jul 30, 2019
Grant date	Jul 30, 2019

Abstract

An electronic device includes a housing, a display panel, a clock generator, a first processor, a graphic RAM, a controller, an antenna element, a second processor, and a memory. The first processor is configured to generate a clock which does not interfere with harmonics of frequencies at which the electronic device transmits or receives signals through the antenna element.

First claim

What is claimed is:

1. An electronic device comprising:
a housing including a first surface, a second surface facing away from the first surface, and a side surface surrounding a space between the first surface and the second surface;
a display panel exposed through the first surface;
a clock generator positioned within the housing, and configured to generate a first clock;
a first processor configured to generate first image data and to transmit the first image data based on the first clock;
a graphic RAM configured to receive the first image data from the first processor and to store the first image data;
a controller electrically connected with the graphic RAM, and configured to select at least a portion of the first image data stored in the graphic RAM and to output the selected portion of the first image data on the display panel;
an antenna element including at least a portion of the housing or positioned within the housing;
a second processor configured to feed the antenna element and to transmit or receive a signal in a first frequency band based on an electrical path formed through the antenna element; and
a memory configured to store state data indicating whether a frequency band of a signal which the second processor transmits or receives is changed,
wherein the first processor is configured to:
allow the electronic device to enter a first state, in which at least a part of the first processor is turned off, based on a number of frames through which the selected portion of the first image data is output;
generate second image data when a specified condition for outputting the second image data is satisfied;
perform a determination to obtain a result of whether the second processor transmits or receives a signal in a second frequency band, based on the state data;
set a second clock through the clock generator, when the determination result indicates that the frequency band of the signal which the second processor transmits or receives is changed;
allow the electronic device to enter a second state in which the at least a part turned off is turned on;
transmit the second image data to the graphic RAM based on the second clock in the second state; and
output at least a portion of the second image data on the display panel through the controller,
wherein the second clock is mapped onto the second frequency band.

2. The electronic device of claim 1 , wherein the first processor is configured to:
allow the electronic device to enter the first state when the number of frames is not smaller than a specified number.

3. The electronic device of claim 1 , wherein the first processor includes:
a display controller configured to generate the first image data;
a transmit module configured to transmit the first image data to the graphic RAM; and
a display controller driver electrically connected with the display controller and the transmit module.

4. The electronic device of claim 3 , wherein the display controller driver is configured to:
turn off the display controller and the transmit module when the electronic device enters the first state.

5. The electronic device of claim 3 , wherein the display controller driver is configured to:
generate the second image data and set the second clock, when the electronic device enters the first state.

6. The electronic device of claim 3 , wherein the display controller driver is configured to:
turn on the display controller and the transmit module when the electronic device enters the second state.

7. The electronic device of claim 3 , wherein, in the second state, the transmit module transmits the second image data to the graphic RAM based on the second clock.

8. The electronic device of claim 1 , wherein the memory is configured to:
store a table in which clocks to be generated by the clock generator are mapped onto frequency bands of a signal to be transmitted/received by the second processor.

9. The electronic device of claim 8 , wherein the first processor is configured:
set the second clock based on the table.

10. The electronic device of claim 1 , wherein the first processor corresponds to an application processor, and
wherein the second processor corresponds to a communication processor.

11. The electronic device of claim 1 , wherein the first processor is configured to:
generate the second image data based on a user input for outputting the second image data.

12. An electronic device comprising:
a housing including a first surface, a second surface facing away from the first surface, and a side surface surrounding a space between the first surface and the second surface;
a display panel exposed through the first surface;
a clock generator positioned within the housing, and configured to generate a first clock;
a first processor configured to generate first image data and to transmit the first image data based on the first clock;
a graphic RAM configured to receive the first image data from the first processor and to store the first image data;
a controller electrically connected with the graphic RAM, and configured to select at least a portion of the first image data stored in the graphic RAM and to output the selected portion of the first image data on the display panel;
a plurality of antenna elements including at least a portion of the housing or positioned within the housing;
a second processor configured to feed at least some of the antenna elements and to transmit or receive first group signals based on electrical paths respectively formed through the fed antenna elements; and
a memory configured to store state data indicating whether a frequency band of signals which the second processor transmits or receives is changed,
wherein the first processor is configured to:
allow the electronic device to enter a first state, in which at least a part of the first processor is turned off, based on a number of frames through which the selected portion of the first image data is output;
generate second image data when a specified condition for outputting the second image data is satisfied;
perform a determination to obtain a result of whether the second processor transmits or receives second group signals, based on the state data;
set a second clock through the clock generator, when the determination result indicates that the frequency band of the signals which the second processor transmits or receives is changed;
allow the electronic device to enter a second state in which the at least a part turned off is turned on;
transmit the second image data to the graphic RAM based on the second clock in the second state; and
output at least a portion of the second image data on the display panel through the controller,
wherein the second clock is mapped onto a frequency band of each of the second group signals.

13. The electronic device of claim 12 , wherein the side surface includes a first edge facing a first direction and having a first length, a second edge being in parallel with the first edge and having the first length, a third edge connecting one end of the first edge and one end of the second edge, and a fourth edge being in parallel with the third edge and connecting an opposite end of the first edge and an opposite end of the second edge, and
wherein the antenna elements include a first antenna element including at least a portion of the first edge, and a second antenna element including at least a portion of the second edge.

14. The electronic device of claim 13 , wherein the second processor transmits or receives a signal in a first frequency band based on a first electrical path formed through the first ant

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Jin Hyun
• Kim Tae Hoon

Classifications

• G09G2320/0247

  Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G5/00

  Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators (image data processing or generation, in general G06T) · CPC title

• G09G2330/06

  Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation · CPC title

• H04B15/04

  the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder · CPC title