Clock generation circuit and method thereof

Patent metadata

Field	Value
Publication number	US-9564910-B2
Application number	US-201514698468-A
Country	US
Kind code	B2
Filing date	Apr 28, 2015
Priority date	May 5, 2014
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

This invention discloses a clock generation circuit and a clock generation method for generating a clock. The clock generation circuit includes a reference clock generation circuit, which is installed in a chip for independently generating a reference clock; a temperature sensor for sensing an ambient temperature to generate temperature information; a temperature compensation module, coupled to the temperature sensor, for generating a temperature compensation coefficient according to the temperature information; and a clock adjusting circuit, coupled to the clock generation circuit, for generating the clock according to the reference clock and the temperature compensation coefficient. The temperature compensation module generates the temperature compensation coefficient dynamically such that the frequency of the clock approaches a target frequency and does not substantially vary with the temperature.

First claim

What is claimed is:

1. A clock generation circuit for generating a clock comprising:
a reference clock generation circuit, which is installed in a chip for independently generating a reference clock;
a temperature sensor for sensing an ambient temperature to generate temperature information;
a temperature compensation module, coupled to the temperature sensor, for generating a temperature compensation coefficient according to the temperature information; and
a clock adjusting circuit, coupled to the reference clock generation circuit, for generating the clock according to the reference clock and the temperature compensation coefficient;
wherein, the temperature compensation module generates the temperature compensation coefficient dynamically so that a frequency of the clock approaches a target frequency and does not substantially vary with the temperature.

2. The clock generation circuit of claim 1 , wherein a variation in the frequency of the reference clock with temperature shows a linear relationship and the temperature compensation module generates the temperature compensation coefficient according to the linear relationship.

3. The clock generation circuit of claim 2 , wherein the temperature compensation module is implemented by firmware and calculates the temperature compensation coefficient every predetermined period according to the temperature information and the linear relationship.

4. The clock generation circuit of claim 2 , wherein the temperature compensation module is implemented by hardware and updates the temperature compensation coefficient in real-time according to the temperature information and the linear relationship.

5. The clock generation circuit of claim 1 , wherein the clock adjusting circuit comprises:
a setting circuit, coupled to the temperature compensation module, for generating a setting value according to the temperature compensation coefficient; and
a frequency synthesizer, coupled to the reference clock generation circuit and the setting circuit, for generating the clock according to the setting value and the reference clock.

6. The clock generation circuit of claim 5 , wherein the temperature compensation module further refers to a reference value to generate the temperature compensation coefficient, and the reference value corresponds to the setting value at a predetermined temperature when the frequency of the clock is substantially identical to the target frequency.

7. The clock generation circuit of claim 5 , wherein the frequency synthesizer further comprises:
a frequency divider, for dividing the frequency of the clock according to the setting value such that a ratio of the frequency of the clock to the frequency of the reference clock corresponds to the setting value.

8. The clock generation circuit of claim 1 , wherein the temperature sensor comprises:
a first BJT, having its emitter coupled to a first current source and its base and collector coupled to a reference level;
a second BJT, having its emitter coupled to a second current source and its base and collector coupled to the reference level; and
a comparator, having one input coupled to the emitter of the first BJT and the other input coupled to the emitter of the second BJT, and its output outputting a comparison value; and
a processing circuit, coupled to the comparator, for converting the comparison value to the temperature information.

9. The clock generation circuit of claim 1 being applied to an image processing chip, which processes a VGA signal according to the clock to determine a display mode of the VGA signal.

10. A clock generation method for generating a clock comprising:
generating a reference clock independently inside a chip;
sensing an ambient temperature to generate temperature information;
generating a temperature compensation coefficient according to the temperature information; and
generating the clock according to the reference clock and the temperature compensation coefficient;
wherein, the temperature compensation coefficient is generated dynamically so that a frequency of the clock approaches a target frequency and does not substantially vary with the temperature.

11. The clock generation method of claim 10 , wherein a variation in the frequency of the reference clock with temperature shows a linear relationship and the step of generating the temperature compensation coefficient according to the temperature information generates the temperature compensation coefficient according to the linear relationship.

12. The clock generation method of claim 11 , wherein the step of generating the temperature compensation coefficient according to the temperature information calculates the temperature compensation coefficient every predetermined period according to the temperature information and the linear relationship.

13. The clock generation method of claim 11 , wherein the step of generating the temperature compensation coefficient according to the temperature information updates the temperature compensation coefficient in real-time according to the temperature information and the linear relationship.

14. The clock generation method of claim 10 , wherein the step of generating the clock according to the reference clock and the temperature compensation coefficient comprises:
generating a setting value according to the temperature compensation coefficient; and
generating the clock according to the setting value and the reference clock.

15. The clock generation method of claim 14 , wherein the step of generating the temperature compensation coefficient according to the temperature information further refers to a reference value to generate the temperature compensation coefficient and the reference value corresponds to the setting value at a predetermined temperature when the frequency of the clock is substantially identical to the target frequency.

16. The clock generation method of claim 10 , further comprising:
dividing the frequency of the clock such that the frequency of the clock approaches the target frequency.

17. The clock generation method of claim 10 being applied to an image processing chip, which processes a VGA signal according to the clock to determine a display mode of the VGA signal.

Assignees

• Realtek Semiconductor Corp

Inventors

• Yang Chih-Yuan
• Wu Cheng-Hua
• Kung Wen-Hsia

Classifications

• H03L1/027

  by using frequency conversion means which is variable with temperature, e.g. mixer, frequency divider, pulse add/subtract logic circuit (H03L1/023, H03L1/026 take precedence) · CPC title

• H03L7/197 Primary

  a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division {(H03L7/1806 takes precedence)} · CPC title

• H03L7/081

  provided with an additional controlled phase shifter {(H03L7/0998 takes precedence)} · CPC title

• H03L7/1974

  for fractional frequency division · CPC title