Intelligent packet aggregation

Patent metadata

Field	Value
Publication number	US-10362149-B2
Application number	US-201615396196-A
Country	US
Kind code	B2
Filing date	Dec 30, 2016
Priority date	Dec 30, 2016
Publication date	Jul 23, 2019
Grant date	Jul 23, 2019

Abstract

Various systems and methods for implementing intelligent packet aggregation are provided herein. A network interface device for implementing intelligent packet aggregation including a packet parser to receive a plurality of packets and route each packet of the plurality of packets to a queue of a plurality of queues, the packets divided among the queues based on the packets' characteristics; and a coordinator circuit to: interface with a processing element to determine a current operational state of the processing element; select a queue from the plurality of queues based on the current operational state of the processing element; and forward a number of packets from the selected queue to the processing element.

First claim

What is claimed is:

1. A network interface device for implementing intelligent packet aggregation, the network interface device comprising:
a packet parser to receive a plurality of packets and route each packet of the plurality of packets to a queue of a plurality of queues, the packets divided among the queues based on the packets' characteristics; and
a coordinator circuit to:
interface with a processing element to determine a current operational state of the processing element;
select a first queue from the plurality of queues based on the current operational state of the processing element; and
forward a number of packets from the selected first queue to the processing element,
wherein to select the first queue from the plurality of queues, the coordinator circuit is to:
determine a current priority associated with each queue of a set of queues of the plurality of queues; and
select the first queue as the one with a highest priority of the current priorities of the set of queues from the set of queues; and

decrease the current priority of a second queue in the set of queues when the current operational state indicates that the processing element is not currently active and unable to process packets stored in the second queue.

2. The device of claim 1 , wherein the processing element comprises a virtual machine.

3. The device of claim 1 , wherein the processing element comprises a field-programmable gate array (FPGA) program.

4. The device of claim 1 , wherein the packet parser includes a TCP offload engine to inspect the plurality of packets.

5. The device of claim 1 , wherein the packet parser is to:
attempt to identify a queue of the plurality of queues that corresponds to a particular packet;
allocate a new queue when the identification fails; and
store the particular packet in the new queue.

6. The device of claim 1 , wherein the current operational state of the processing element comprises a current operating thread.

7. The device of claim 1 , wherein the current operational state of the processing element comprises a current operating process.

8. The device of claim 1 , wherein the current operational state of the processing element comprises a current operating virtual machine.

9. The device of claim 1 , wherein the current operational state of the processing element comprises a current FPGA configuration.

10. The device of claim 1 , wherein the current priority of the first queue is increased when the current operational state indicates that the processing element is able to process packets stored in the first queue.

11. The device of claim 1 , wherein to forward the number of packets from the selected first queue to the processing element, the coordinator circuit is to enforce a traffic regulation policy while forwarding the number of packets.

12. A method of implementing intelligent packet aggregation, the method comprising:
receiving, at a packet parser, a plurality of packets and route each packet of the plurality of packets to a queue of a plurality of queues, the packets divided among the queues based on the packets' characteristics;
interfacing with a processing element to determine a current operational state of the processing element;
selecting a first queue from the plurality of queues based on the current operational state of the processing element; and
forwarding a number of packets from the selected first queue to the processing element,
wherein selecting the first queue from the plurality of queues comprises:
determining a current priority associated with each queue of a set of queues of the plurality of queues; and
selecting the first queue as the one with a highest priority of the current priorities of the set of queues from the set of queues; and

decreasing the current priority of a second queue in the set of queues when the current operational state indicates that the processing element is not currently active and unable to process packets stored in the second queue.

13. The method of claim 12 , wherein the packet parser includes a TCP offload engine to inspect the plurality of packets.

14. The method of claim 12 , further comprising:
attempting to identify a queue of the plurality of queues that corresponds to a particular packet;
allocating a new queue when the identification fails; and
storing the particular packet in the new queue.

15. The method of claim 12 , wherein the current operational state of the processing element comprises a current operating thread.

16. The method of claim 12 , wherein the current operational state of the processing element comprises a current operating process.

17. The method of claim 12 , wherein the current operational state of the processing element comprises a current operating virtual machine.

18. The method of claim 12 , wherein the current operational state of the processing element comprises a current FPGA configuration.

19. The method of claim 12 , wherein the current priority of the first queue is increased when the current operational state indicates that the processing element is able to process packets stored in the first queue.

20. At least one non-transitory machine-readable medium including instructions for implementing intelligent packet aggregation, which when executed by a machine, cause the machine to:
receive, at a packet parser, a plurality of packets and route each packet of the plurality of packets to a queue of a plurality of queues, the packets divided among the queues based on the packets' characteristics;
interface with a processing element to determine a current operational state of the processing element;
select a first queue from the plurality of queues based on the current operational state of the processing element; and
forward a number of packets from the selected first queue to the processing element,
wherein to select the first queue from the plurality of queues, the instructions cause the machine to:
determine a current priority associated with each queue of a set of queues of the plurality of queues; and
select the first queue as the one with a highest priority of the current priorities of the set of queues from the set of queues; and

decrease the current priority of a second queue in the set of queues when the current operational state indicates that the processing element is not currently active and unable to process packets stored in the second queue.

21. The non-transitory medium of claim 20 , further comprising instructions to:
attempt to identify a queue of the plurality of queues that corresponds to a particular packet;
allocate a new queue when the identification fails; and
store the particular packet in the new queue.

Assignees

• Intel Corp

Inventors

• Biederman Dan
• Orr Michael

Classifications

• H04L69/16

  Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP] · CPC title

• H04L47/22

  Traffic shaping · CPC title

• H04L49/9005

  using dynamic buffer space allocation · CPC title

• H04L47/625

  for service slots or service orders · CPC title

• H04L69/321

  Interlayer communication protocols or service data unit [SDU] definitions; Interfaces between layers · CPC title