Memory modules, memory systems including the same, and methods of calibrating multi-die impedance of the memory modules

Patent metadata

Field	Value
Publication number	US-10361699-B2
Application number	US-201815922332-A
Country	US
Kind code	B2
Filing date	Mar 15, 2018
Priority date	Aug 10, 2017
Publication date	Jul 23, 2019
Grant date	Jul 23, 2019

Abstract

A memory module includes an external resistor and a plurality of memory devices commonly connected to the external resistor. Each of the memory devices includes a first reception pad and a first transmission pad. The first reception pad is associated with receiving an impedance calibration command and the first transmission pad is associated with transmitting the impedance calibration command. Each of the memory devices transfers the impedance calibration command to a first memory device which is selected as a master among the plurality of memory devices through a ring topology. The first memory device performs an impedance calibration operation, determines a resistance and a target output high level voltage of an output driver in response to the impedance calibration command, and transfers the impedance calibration command to a second memory device after performing the impedance calibration operation.

First claim

What is claimed is:

1. A memory module comprising:
an external resistor formed in a module board; and
a plurality of memory devices including a first memory device and a second memory device, and commonly connected to the external resistor,
wherein each of the plurality of memory devices comprises:
an impedance pad connected to the external resistor; a selection pad;
a first reception pad associated with receiving an impedance calibration command;
a first transmission pad associated with transmitting the impedance calibration command; and
an impedance calibration circuit connected to the first reception pad, the first transmission pad, the impedance pad, and the selection pad, wherein each of the plurality of memory device is configured to transfer the impedance calibration command to the first memory device, which is selected as a master, among the plurality of memory devices through a ring topology constituted by the first reception pad and the first transmission pad,
wherein the first memory device is configured to perform an impedance calibration operation for the first memory device, to determine a resistance and a target output high level (VOH) voltage of an output driver, in response to the impedance calibration command, and is configured to transfer the impedance calibration command to the second memory device adjacent to the first memory device through the first transmission pad of the first memory device after performing the impedance calibration operation for the first memory device,
wherein when the selection pad of the first memory device is connected to a ground voltage or a power supply voltage, the section pad of the second memory device is floated, and
wherein when the selection pad of the first memory device is floated, the selection pad of the second memory device is connected to the ground voltage.

2. The memory module of claim 1 , wherein the plurality of memory devices further includes a third memory device,
wherein the second memory device is configured to perform the impedance calibration operation for the second memory device in response to the impedance calibration command and is configured to transfer the impedance calibration command to the third memory device adjacent to the second memory device through the first transmission pad of the second memory device after performing the impedance calibration operation for the second memory device, and
wherein the third memory device is connected to the first transmission pad of the second memory device.

3. The memory module of claim 1 ,
wherein the impedance calibration circuit comprises:
a detector connected to the selection pad, and configured to generate a detection signal;
a command controller connected to the first reception pad and the first transmission pad, wherein the command controller is configured to receive the impedance calibration command from one of the first reception pad and a corresponding command decoder; and
a calibration circuit connected to the external resistor through the impedance pad, wherein the calibration circuit is configured to perform the impedance calibration operation in response to a calibration enable signal from the command controller to output a pull-up control code and a pull-down control code to the output driver, and is configured to provide the command controller with a first comparison signal and a second comparison signal which indicate a completion of the impedance calibration operation.

4. The memory module of claim 3 , wherein:
the detector is configured to provide the command controller with the detection signal having a first logic level when a corresponding memory device is selected as the master; and
the detector is configured to provide the command controller with the detection signal having a second logic level when the corresponding memory device is not selected as the master.

5. The memory module of claim 3 , wherein:
the command controller is configured to enable the calibration enable signal and provide the calibration enable signal to the calibration circuit when the detection signal indicates that a corresponding memory device is selected as the master and the impedance calibration command is received from the first reception pad or the corresponding command decoder;
the calibration circuit is configured to perform the impedance calibration operation in response to the impedance calibration command, and is configured to transit logic levels of the first comparison signal and the second comparison signal when the impedance calibration operation is completed; and
the command controller is configured to change tag information of the impedance calibration command to a first level based on transitions of the first comparison signal and the second comparison signal and is configured to transfer the impedance calibration command to an adjacent memory device through the first transmission pad.

6. The memory module of claim 3 , wherein:
the command controller is configured to enable the calibration enable signal and provide the calibration enable signal to the calibration circuit when the detection signal indicates that a corresponding memory device is not selected as the master, tag information of the impedance calibration command has a first logic level, and the impedance calibration command is received from the first reception pad;
the calibration circuit is configured to perform the impedance calibration operation in response to the impedance calibration command, and is configured to transit logic levels of the first comparison signal and the second comparison signal when the impedance calibration operation is completed; and
the command controller is configured to transfer the impedance calibration command to an adjacent memory device through the first transmission pad based on transitions of the first comparison signal and the second comparison signal.

7. The memory module of claim 3 , wherein:
the command controller is configured to disable the calibration enable signal and provide the calibration enable signal to the calibration circuit when the detection signal indicates that a corresponding memory device is not selected as the master, tag information of the impedance calibration command has a second logic level, and the impedance calibration command is received from the first reception pad or the corresponding command decoder; and
the command controller is configured to transfer the impedance calibration command to an adjacent memory device through the first transmission pad.

8. The memory module of claim 3 , wherein the command controller comprises:
a path decision logic configured to receive the impedance calibration command from one of the first reception pad and the corresponding command decoder and is configured to provide a path information signal that indicates a reception path of the impedance calibration command and tag information;
a signal generator configured to determine a logic level of the calibration enable signal in response to the detection signal and the path information signal to output the calibration enable signal; and
a state machine configured to determine a logic level of an internal calibration mask signal based on the calibration enable signal and transitions of the first comparison signal and the second comparison signal,
wherein the signal generator is further configured to provide the path decision logic with a path control signal to control a transfer of the impedance calibration command and a change of the tag information based on a state of the state machine.

9. The memory module of claim 3 , wherein the calibration circuit comprises:
a first code generator configured to generate the pull-up control code obtained from a result of comparing t

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jun-Ha
• LEE Chang-kyo
• Eom Yoon-Joo

Classifications

• G11C7/1084

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• H03K19/0005 Primary

  Modifications of input or output impedance · CPC title

• G11C7/1057

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title