Semiconductor device having junctionless vertical gate transistor and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10361206-B2
Application number	US-201514825030-A
Country	US
Kind code	B2
Filing date	Aug 12, 2015
Priority date	Mar 12, 2012
Publication date	Jul 23, 2019
Grant date	Jul 23, 2019

Abstract

A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a plurality of bit lines buried within a substrate and extending along a first direction;
forming a plurality of active pillars over the bit lines, each of the plurality of active pillars including a first impurity region contacting the bit line and second and third impurity regions sequentially formed on the first impurity region; and
forming gate electrodes over sidewalls of the second impurity regions, the gate electrodes extending in a second direction crossing the bit lines,
wherein forming the plurality of active pillars comprises:
forming a semiconductor growth layer including a first region layer, a second region layer, and a third region layer over the bit lines and the substrate;
patterning the semiconductor growth layer to form a plurality of pillars extending along the first direction, each of the plurality of pillars including first to third region patterns extending along the first direction;
implanting the first, second, and third region patterns of the plurality of pillars with impurities having substantially the same polarity; and
patterning the plurality of pillars to form a plurality of trenches extending along the second direction after the implantation to form the active pillars so that first and second sidewalls of the active pillars are exposed by the trenches, each of the trenches exposing top surfaces of the first impurity regions of the plurality of active pillars, and

wherein a top surface of the bit lines is level with a top surface of the substrate, and
wherein substantially no junction is formed among the first, the second, and the third impurity regions to form a junctionless vertical gate transistor.

2. The method according to claim 1 , wherein forming the gate electrodes comprises:
forming a gate insulation layer including a first portion and a second portion, the first portion being disposed over the exposed top surfaces of the first impurity regions and the second portion being disposed over the first and the second sidewalls of the active pillars; and
forming the gate electrodes over the gate insulation layer to be located over the sidewalls of the second impurity regions of the active pillars.

3. The method according to claim 1 , wherein the impurities are implanted by any of multi ion implantation, tilt ion implantation, orient ion implantation, and a combination thereof.

4. The method according to claim 1 , wherein each of the first, second, and third impurity regions is doped with a doping concentration ranging from 8×10 18 to 3×10 19 atom/cm 3 .

5. The method according to claim 1 , wherein the plurality of bit lines are formed by performing ion implantation into the substrate.

6. The method according to claim 1 , wherein forming the plurality of bit lines comprises:
forming a plurality of recesses in the substrate;
forming insulation layers along bottom surfaces and sidewalls of the plurality of recesses; and
filling the plurality of recesses with a conductive material so that the insulation layers are interposed between the bit lines and the substrate.

7. The method according to claim 6 , wherein the conductive material includes any of metal, metal silicide, polysilicon, and a combination thereof.

8. The method according to claim 1 , wherein the first impurity region is formed on a corresponding bit line and extends along the first direction, the second impurity regions are formed on the first impurity region, and the third impurity regions are formed on the second impurity regions, respectively, the second impurity regions are arranged at a constant interval over the first impurity region.

9. The method according to claim 1 , wherein each of the gate electrodes extends along a row of second impurity regions so that the gate electrode is formed over sidewalls of the second impurity regions in the row, each of the sidewalls of the second impurity regions in the row being disposed between two second impurity regions that are adjacent in a corresponding active pillar of the active pillars.

Assignees

• Sk Hynix Inc
• Korea Advanced Inst Sci & Tech

Inventors

• Moon Jung-Min
• Kim Tae-Kyun
• Lee Seok-Hee

Classifications

• H01L29/7828

  Electricity · mapped topic

• H01L29/7827

  Electricity · mapped topic

• H01L27/10814 Primary

  Electricity · mapped topic

• H01L29/105

  Electricity · mapped topic

• H01L29/4236

  Electricity · mapped topic