Semiconductor devices and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-10361194-B2
Application number	US-201615335984-A
Country	US
Kind code	B2
Filing date	Oct 27, 2016
Priority date	Oct 30, 2015
Publication date	Jul 23, 2019
Grant date	Jul 23, 2019

Abstract

Semiconductor device having less defects in a gate insulating film and improved reliability and methods of forming the semiconductor devices are provided. The semiconductor devices may include a gate insulating film on a substrate and a gate electrode structure on the gate insulating film. The gate electrode structure may include a lower conductive film, a silicon oxide film, and an upper conductive film sequentially stacked on the gate insulating film. The lower conductive film may include a barrier metal layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a fin-shaped active region protruding from a substrate;
a gate insulating layer on the substrate; and
a gate electrode structure that extends along three sides of the fin-shaped active region, on the gate insulating layer,
wherein the gate electrode structure comprises a lower conductive layer and an upper conductive layer sequentially stacked on the gate insulating layer and a silicon oxide layer between the lower conductive layer and the upper conductive layer, and the lower conductive layer comprises a barrier metal layer,
wherein the silicon oxide layer extends along a sidewall and a bottom surface of the upper conductive layer, and
wherein the three sides of the fin-shaped active region comprise top, right, and left sides of the fin-shaped active region.

2. The semiconductor device of claim 1 , wherein the gate electrode structure further comprises a semiconductor liner between the silicon oxide layer and the lower conductive layer.

3. The semiconductor device of claim 2 , wherein the semiconductor liner comprises a silicon layer.

4. The semiconductor device of claim 1 , further comprising an interlayer insulating layer on the substrate,
wherein the interlayer insulating layer comprises a trench, and
wherein the gate insulating layer, the lower conductive layer, and the silicon oxide layer extend along a sidewall and a bottom surface of the trench.

5. The semiconductor device of claim 1 , wherein a lower portion of the fin-shaped active region is wider than an upper portion of the fin-shaped active region.

6. A semiconductor device comprising: a substrate comprising a first region and a second region;
a first fin-shaped active region protruding from the first region of the substrate;
a second fin-shaped active region protruding from the second region of the substrate; a first gate insulating layer on the first fin-shaped active region;
a first gate electrode structure that extends along three sides of the first fin-shaped active region, on the first gate insulating layer, the first gate electrode structure comprising a first lower conductive layer, a first silicon oxide layer and a first upper conductive layer sequentially stacked on the first gate insulating layer, and the first lower conductive layer comprising a first barrier metal layer;
a second gate insulating layer on the second fin-shaped active region; and
a second gate electrode structure that extends along three sides of the second fin-shaped active region, on the second gate insulating layer, the second gate electrode structure comprising a second lower conductive layer and a second upper conductive layer sequentially stacked on the second gate insulating layer,
wherein the first silicon oxide layer extends along a sidewall and a bottom surface of the first upper conductive layer, wherein the three sides of the first fin-shaped active region comprise top, right, and left sides of the first fin-shaped active region, and wherein the three sides of the second fin-shaped active region comprise top, right, and left sides of the second fin-shaped active region.

7. The semiconductor device of claim 6 , wherein the second gate electrode structure further comprises a second silicon oxide layer.

8. The semiconductor device of claim 7 , wherein the second silicon oxide layer is disposed between the second lower conductive layer and the second upper conductive layer.

9. The semiconductor device of claim 7 , wherein the second gate electrode structure further comprises a semiconductor liner between the second silicon oxide layer and the second gate insulating layer.

10. The semiconductor device of claim 7 , wherein the second gate electrode structure further comprises a semiconductor liner between the second lower conductive layer and the second upper conductive layer.

11. The semiconductor device of claim 10 , wherein the second gate electrode structure does not include a silicon oxide layer between the semiconductor liner and the second upper conductive layer.

12. The semiconductor device of claim 7 , further comprising an interlayer insulating layer on the substrate,
wherein the interlayer insulating layer comprises a first trench and a second trench,
wherein the first gate insulating layer, the first lower conductive layer, and the first silicon oxide layer extend along a sidewall and a bottom surface of the first trench, and
wherein the second gate insulating layer, the second lower conductive layer, and the second silicon oxide layer extend along a sidewall and a bottom surface of the second trench.

13. The semiconductor device of claim 6 , wherein the second gate electrode structure does not include a silicon oxide layer between the second lower conductive layer and the second upper conductive layer.

14. The semiconductor device of claim 6 , wherein the first gate electrode structure further comprises a semiconductor liner between the first silicon oxide layer and the first lower conductive layer.

15. The semiconductor device of claim 6 , further comprising:
a first source/drain region adjacent the first gate electrode structure, in the first fin-shaped active region; and
a second source/drain region adjacent the second gate electrode structure, in the second fin-shaped active region.

16. A semiconductor device comprising:
a fin-shaped active region protruding from a substrate;
an interlayer insulating layer on the substrate, the interlayer insulating layer comprising a trench that crosses the fin-shaped active region;
a gate insulating layer extending along a sidewall and a bottom surface of the trench; and
a gate electrode structure that extends along three sides of the fin-shaped active region on the gate insulating layer in the trench,
wherein the gate electrode structure comprises an insertion insulating layer that is spaced apart from the gate insulating layer and is on the sidewall and the bottom surface of the trench,
wherein the insertion insulating layer comprises an oxide, oxynitride or nitride of a semiconductor material, and wherein the three sides of the fin-shaped active region comprise top, right, and left sides of the fin-shaped active region.

17. The semiconductor device of claim 16 , wherein the insertion insulating layer comprises silicon oxide, silicon oxynitride, silicon nitride and/or germanium oxide.

18. The semiconductor device of claim 16 , wherein the gate electrode structure further comprises a semiconductor liner between the insertion insulating layer and the gate insulating layer.

19. The semiconductor device of claim 18 , wherein the semiconductor liner comprises a silicon layer, a silicon germanium layer and/or a germanium layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Moon-Kyu
• Song Jae-Yeol
• Na Hoon-Joo
• Hwang Yoon-Tae
• Yoon Ki-joong
• Hyun Sang-Jin

Classifications

• H10P14/6544

  to change the morphology of the insulating materials, e.g. transformation of an amorphous layer into a crystalline layer · CPC title

• H10P14/6536

  by exposure to radiation, e.g. visible light · CPC title

• H01L29/7854

  Electricity · mapped topic

• H01L21/02345

  Electricity · mapped topic

• H01L29/7856

  Electricity · mapped topic