Microcontroller with digital delay line analog-to-digital converters and digital comparators

Patent metadata

Field	Value
Publication number	US-10355707-B2
Application number	US-201815901294-A
Country	US
Kind code	B2
Filing date	Feb 21, 2018
Priority date	Apr 12, 2016
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

Embodiments of the present disclosure include a microcontroller with a processor core, memory, and a plurality of peripheral devices including a differential digital delay line analog-to-digital converter (ADC). The ADC includes differential digital delay lines and circuit comprising a set of delay elements included in the differential digital delay lines configured to generate data representing an analog to digital conversion of an input. The microcontroller also includes a digital comparator coupled with an output of the ADC and an associated register, wherein at least one output of the digital comparator is configured to directly control another peripheral of the plurality of peripherals.

First claim

The invention claimed is:

1. An apparatus, comprising:
a differential digital delay line analog-to-digital converter (ADC), the ADC comprising:
a plurality of differential digital delay lines; and
a first circuit comprising a set of delay elements included in the differential digital delay lines configured to generate data representing an analog to digital conversion of an input; and

a comparator coupled with an output of the ADC and an associated register, wherein at least one output of the digital comparator is configured to directly control another peripheral;
wherein the other peripheral is a pulse width modulation module and the output of the digital comparator is configured to directly drive voltage adjustments of the pulse width modulation circuit, bypassing software control.

2. The apparatus of claim 1 , comprising a plurality of digital comparators, each digital comparator coupled with an output of the ADC and with an associated register, wherein each digital comparator comprises a first output indicating that the output of the ADC is greater than a value of the associated register and a second output indicating that the output of the ADC is less or equal than the value of the associated register.

3. The apparatus of claim 1 , further comprising an internal bus coupled with the output of digital delay line analog-to-digital converter and a first input of the at least one digital comparator.

4. The apparatus of claim 1 , further comprising a second circuit, the second circuit comprising a set of delay elements configured to calibrate a source to the differential digital delay lines of the differential digital delay line ADC.

5. An apparatus, comprising:
a differential digital delay line analog-to-digital converter (ADC), the ADC comprising:
a plurality of differential digital delay lines; and
a first circuit comprising a set of delay elements included in the differential digital delay lines configured to generate data representing an analog to digital conversion of an input;

a comparator coupled with an output of the ADC and an associated register, wherein at least one output of the digital comparator is configured to directly control another peripheral; and
a second circuit, the second circuit comprising a set of delay elements configured to calibrate a source to the differential digital delay lines of the differential digital delay line ADC.

6. The apparatus of claim 1 , further comprising a plurality of digital comparators, each digital comparator coupled with an output of the ADC and with an associated register, wherein each digital comparator comprises a first output indicating that the output of the ADC is greater than a value of the associated register and a second output indicating that the output of the ADC is less or equal than the value of the associated register.

7. The apparatus of claim 1 , further comprising an internal bus coupled with the output of digital delay line analog-to-digital converter and a first input of the at least one digital comparator.

8. The apparatus of claim 1 , wherein the other peripheral is a pulse width modulation module and the output of the digital comparator is configured to directly drive voltage adjustments of the pulse width modulation circuit, bypassing software control.

9. A microcontroller, comprising:
a processor core;
a memory;
a differential digital delay line analog-to-digital converter (ADC), the ADC comprising:
a plurality of differential digital delay lines; and
a first circuit comprising a set of delay elements included in the differential digital delay lines configured to generate data representing an analog to digital conversion of an input; and

a comparator coupled with an output of the ADC and an associated register, wherein at least one output of the digital comparator is configured to directly control another peripheral;
wherein the other peripheral is a pulse width modulation module and the output of the digital comparator is configured to directly drive voltage adjustments of the pulse width modulation circuit, bypassing software control of the processor core.

10. The microcontroller of claim 9 , further comprising a plurality of digital comparators, each digital comparator coupled with an output of the ADC and with an associated register, wherein each digital comparator comprises a first output indicating that the output of the ADC is greater than a value of the associated register and a second output indicating that the output of the ADC is less or equal than the value of the associated register.

11. The microcontroller of claim 9 , further comprising an internal bus coupled with the output of digital delay line analog-to-digital converter and a first input of the at least one digital comparator.

12. The microcontroller of claim 9 , further comprising a second circuit, the second circuit comprising a set of delay elements configured to calibrate a source to the differential digital delay lines of the differential digital delay line ADC.

13. A microcontroller, comprising:
a memory;
a processor core;
a differential digital delay line analog-to-digital converter (ADC), the ADC comprising:
a plurality of differential digital delay lines; and
a first circuit comprising a set of delay elements included in the differential digital delay lines configured to generate data representing an analog to digital conversion of an input;

a comparator coupled with an output of the ADC and an associated register, wherein at least one output of the digital comparator is configured to directly control another peripheral; and
a second circuit, the second circuit comprising a set of delay elements configured to calibrate a source to the differential digital delay lines of the differential digital delay line ADC.

14. The microcontroller of claim 13 , further comprising a plurality of digital comparators, each digital comparator coupled with an output of the ADC and with an associated register, wherein each digital comparator comprises a first output indicating that the output of the ADC is greater than a value of the associated register and a second output indicating that the output of the ADC is less or equal than the value of the associated register.

15. The microcontroller of claim 13 , further comprising an internal bus coupled with the output of digital delay line analog-to-digital converter and a first input of the at least one digital comparator.

16. The microcontroller of claim 13 , wherein the other peripheral is a pulse width modulation module and the output of the digital comparator is configured to directly drive voltage adjustments of the pulse width modulation circuit, bypassing software control from the processor core.

Assignees

• Microchip Tech Inc

Inventors

• Kris Bryan

Classifications

• H03M1/1057

  by trimming, i.e. by individually adjusting at least part of the quantisation value generators or stages to their nominal values · CPC title

• H03M1/1028

  at two points of the transfer characteristic, i.e. by adjusting two reference values, e.g. offset and gain error (gain setting for range control H03M1/18) · CPC title

• H03M1/38

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title

• H03M1/007 Primary

  among different resolutions · CPC title

• H02M3/156

  with automatic control of output voltage or current, e.g. switching regulators · CPC title