Amplification circuit with split-length compensation scheme

Patent metadata

Field	Value
Publication number	US-10355656-B2
Application number	US-201816021859-A
Country	US
Kind code	B2
Filing date	Jun 28, 2018
Priority date	Jun 29, 2017
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

An amplification circuit includes: a current source; a first input transistor pair suitable for receiving a positive input voltage and having a split-length gate structure; a second input transistor pair suitable for receiving a negative input voltage and having a split-length gate structure; an enable unit suitable for supplying a current from the current source to each of the first input transistor pair and the second input transistor pair in response to an enable signal; a switching unit suitable for coupling a second split gate node between the second input transistor pair to a compensation capacitor node during an activation section of the enable signal; and a compensation driving unit suitable for compensating and driving a first split gate node between the first input transistor pair at an initial stage of the activation section of the enable signal.

First claim

What is claimed is:

1. An amplification circuit, comprising:
a current source;
a first input transistor pair suitable for receiving a positive input voltage and having a split-length gate structure;
a second input transistor pair suitable for receiving a negative input voltage and having a split-length gate structure;
an enable unit suitable for supplying a current from the current source to each of the first input transistor pair and the second input transistor pair in response to an enable signal;
a switching unit suitable for coupling a second split gate node between the second input transistor pair to a compensation capacitor node during an activation section of the enable signal; and
a compensation driving unit suitable for compensating and driving a first split gate node between the first input transistor pair at an initial stage of the activation section of the enable signal.

2. The amplification circuit of claim 1 , further comprising:
an equalizing unit suitable for equalizing the first split gate node and the second split gate node during a deactivation section of the enable signal.

3. The amplification circuit of claim 1 , further comprising:
a first current mirroring transistor coupled to a first output terminal corresponding to the second input transistor pair; and
a second current mirroring transistor coupled to a second output terminal corresponding to the first input transistor pair.

4. The amplification circuit of claim 1 , further comprising:
a secondary amplification unit that are cascode-coupled to a first output terminal corresponding to the second input transistor pair and a second output terminal corresponding to the first input transistor pair.

5. The amplification circuit of claim 1 , wherein the switching unit is controlled based on the enable signal, and includes a first transmission gate coupled between the second split gate node and the compensation capacitor node.

6. The amplification circuit of claim 1 , wherein the compensation driving unit pull-up drives the first split gate node in response to a compensation driving pulse that pulses in the initial stage of the activation section of the enable signal.

7. The amplification circuit of claim 6 , wherein the compensation driving unit includes the PMOS transistor that is coupled between a power source voltage terminal and the first split gate node, and receives the compensation driving pulse through a gate.

8. The amplification circuit of claim 2 , wherein the equalizing unit is controlled based on the enable signal, and includes a second transmission gate coupled between the first split gate node and the second split gate node.

Assignees

• Sk Hynix Inc

Inventors

• Kim Jungung

Classifications

• H03F3/211

  using a combination of several amplifiers (H03F3/60 takes precedence) · CPC title

• H03F1/086 Primary

  with FET's · CPC title

• H03F3/4565

  Controlling the common source circuit of the differential amplifier · CPC title

• H03F3/45192 Primary

  Folded cascode stages · CPC title

• H03F3/45188 Primary

  Non-folded cascode stages · CPC title