Power trench capacitor compatible with deep trench isolation process

Patent metadata

Field	Value
Publication number	US-10355072-B2
Application number	US-201715441776-A
Country	US
Kind code	B2
Filing date	Feb 24, 2017
Priority date	Feb 24, 2017
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

A method for forming a trench capacitor without an additional mask adder and the resulting device are provided. Embodiments include forming a buried implant layer over a substrate; forming an EPI layer over the buried implant layer; forming an oxide layer over the EPI layer; forming a nitride layer over the oxide layer; forming first and second trenches in the nitride layer, the oxide layer, the EPI layer, the buried implant layer and the substrate, the first trench being wider and deeper than the second trench; forming a dielectric layer in the trenches; forming a first polysilicon layer over the dielectric layer in the trenches; removing the first polysilicon layer and the dielectric layer above the EPI layer in the trenches and at a bottom of the first trench; and forming a second polysilicon layer filling the first trench and above the EPI layer in the second trench.

First claim

What is claimed is:

1. A method comprising:
forming a buried implant layer over a substrate;
forming an epitaxial (EPI) layer over the buried implant layer;
forming an oxide layer over the EPI layer;
forming a nitride layer over the oxide layer;
forming a deep trench isolation (DTI) and a DTI-capacitor (DTI-CAP) in the nitride layer, the oxide layer, the EPI layer, the buried implant layer and the substrate, the DTI being wider and deeper than the DTI-CAP;
forming a dielectric layer in the DTI and DTI-CAP;
forming a first polysilicon layer over the dielectric layer in the DTI and DTI-CAP;
removing the first polysilicon layer and the dielectric layer above the EPI layer in the DTI and DTI-CAP and at a bottom of the DTI; and
forming a second polysilicon layer filling the DTI and above the EPI layer in the DTI-CAP,
wherein the EPI layer is a bottom plate of the DTI-CAP and the first and second polysilicon layers are a top plate of the DTI-CAP.

2. The method according to claim 1 , comprising:
forming the dielectric layer and the first polysilicon layer by:
depositing a dielectric material and a first polysilicon material consecutively over the nitride layer and in the DTI and DTI-CAP; and
etching the dielectric material and the first polysilicon material back to an upper surface of the nitride layer.

3. The method according to claim 2 , comprising removing the first polysilicon layer and the dielectric layer above an upper surface of the EPI layer in the DTI and DTI-CAP and at a bottom of the DTI by etching concurrently the dielectric material and the first polysilicon material back to an upper surface of the nitride layer.

4. The method according to claim 3 , comprising etching by a dry etch process.

5. The method according to claim 1 , comprising forming the DTI to a width of about 2 micrometer (μm) and the DTI-CAP to a width of 0.5 μm to 1 μm.

6. The method according to claim 1 , comprising forming the second polysilicon layer by:
depositing a second polysilicon material over the nitride layer, filling the DTI, and above the EPI layer in the DTI-CAP; and
etching the second polysilicon material down to an upper surface of the nitride layer.

7. The method according to claim 6 , comprising etching the second polysilicon material by a dry etch process.

8. The method according to claim 1 , further comprising:
forming the dielectric layer, the first polysilicon layer and the second polysilicon layer using a furnace oxidation process and a sub-atmospheric chemical vapor deposition (SACVD) process.

9. The method according to claim 1 , wherein the dielectric layer comprises linear oxide and tetraethylorthosilicate (TEOS).

10. The method according to claim 1 , comprising forming the dielectric layer to a thickness of 2,000 Angstrom (Å) to 4,000 Å.

11. The method according to claim 1 , comprising forming the first polysilicon layer to a thickness of 15,000 Å to 20,000 Å.

12. The method according to claim 1 , comprising forming the second polysilicon layer to a thickness of 10,000 Å to 15,000 Å.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Wang Zeng
• Si Wei
• Koo Jeoung Mo
• Verma Purakh Raj

Classifications

• H10P14/42

  using a gas or vapour · CPC title

• H10W10/0143

  comprising concurrently refilling multiple trenches having different shapes or dimensions · CPC title

• H10W10/031

  of isolation regions comprising PN junctions · CPC title

• H10W10/30

  Isolation regions comprising PN junctions · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title