Display panel and display apparatus

US10355030B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10355030-B2
Application numberUS-201815869136-A
CountryUS
Kind codeB2
Filing dateJan 12, 2018
Priority dateDec 30, 2016
Publication dateJul 16, 2019
Grant dateJul 16, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display panel and a display apparatus are provided. The display panel includes: a substrate; multiple first-layer wires disposed on the substrate; and an insulating dielectric layer disposed on the first-layer wires. A dielectric constant of the insulating dielectric layer is higher than dielectric constants of silicon oxide layer and silicon nitride layer. The insulating dielectric layer includes a composition. The composition includes a first component and a second component. A dielectric constant of the first component is lower than the dielectric constants of silicon oxide layer and silicon nitride layer. A dielectric constant of the second component is higher than the dielectric constants of silicon oxide layer and silicon nitride layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A display apparatus comprising a display panel, the display panel comprising: a substrate; a plurality of first-layer wires, disposed on the substrate; an insulating dielectric layer, disposed on the plurality of first-layer wires, wherein a dielectric constant of the insulating dielectric layer is higher than dielectric constants of silicon oxide and silicon nitride, the insulating dielectric layer comprises a composition, the composition comprises a first component and a second component, a dielectric constant of the first component is lower than the dielectric constants of silicon oxide and silicon nitride, a dielectric constant of the second component is higher than the dielectric constants of silicon oxide and silicon nitride, wherein an amorphous silicon layer is disposed on the insulating dielectric layer and corresponding to a gate conductor segment, an ohmic contact layer is disposed on and corresponding to the amorphous silicon layer, a source conductor segment and a drain conductor segment are separated from each other and disposed on the ohmic contact layer, a channel is disposed between the source conductor segment and the drain conductor segment, the channel passes through the ohmic contact layer, the amorphous silicon layer is located at the bottom of the channel, a width of the source conductor segment and the drain conductor segment as a whole is greater than a width of the amorphous silicon layer, a width of the amorphous silicon layer is equal to that of the ohmic contact layer, a second insulating layer is disposed on the source conductor segment and the drain conductor segment, a pixel electrode layer is disposed on the second insulating layer, the second insulating layer is provided with a via hole corresponding to the drain conductor segment, and the pixel electrode layer is connected with the drain conductor segment by the via hole, wherein a relative dielectric constant of the second insulating layer is 1.4˜2.4. 2. The display apparatus as claimed in claim 1 , wherein a relative dielectric constant of the second insulating layer is lower than relative dielectric constants of silicon nitride and silicon oxide, the second insulating layer comprises a mesoporous silica structure. 3. The display apparatus as claimed in claim 2 , wherein the mesoporous silica structure comprises a plurality of subunits, each of the plurality of the subunits comprises seven subparts arranged in such a manner that one subpart is surrounded and connected by the other six subparts.

Assignees

Inventors

Classifications

  • in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

  • Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

  • Storage capacitors associated with the pixel electrode · CPC title

  • Through-hole connection of the pixel electrode to the active element through an insulation layer · CPC title

  • Electricity · mapped topic

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Frequently asked questions

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What does patent US10355030B2 cover?
A display panel and a display apparatus are provided. The display panel includes: a substrate; multiple first-layer wires disposed on the substrate; and an insulating dielectric layer disposed on the first-layer wires. A dielectric constant of the insulating dielectric layer is higher than dielectric constants of silicon oxide layer and silicon nitride layer. The insulating dielectric layer inc…
Who is the assignee on this patent?
Hkc Corp Ltd, Chongqing Hkc Optoelectronics Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification H01L27/1255. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 16 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).