Memory devices including one-time programmable memory cells

Patent metadata

Field	Value
Publication number	US-10355004-B2
Application number	US-201514845321-A
Country	US
Kind code	B2
Filing date	Sep 4, 2015
Priority date	Sep 29, 2014
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

A memory device including one-time programmable memory cells has a semiconductor substrate with a write region and a read region, a write gate provided on the write region, a read gate provided on the read region, first and second junction patterns provided at both sides of the read gate, and insulating dielectric patterns interposed between the write and read gates and the semiconductor substrate. The read region may have a different conductivity type from the first and second junction patterns, and the write region may have the same conductivity type as the first and second junction patterns.

First claim

What is claimed is:

1. A memory device, comprising:
a semiconductor substrate having a first conductivity type;
an impurity region in a top region of the semiconductor substrate, wherein the impurity region has a second conductivity type that is different from the first conductivity type;
a write gate on a top surface of the impurity region;
a read gate on a top surface of the semiconductor substrate;
a first junction pattern at and directly adjacent a first side of the read gate; and
a second junction pattern at and directly adjacent a second side of the read gate and directly adjacent a first side of the write gate,
wherein each of the first and second junction patterns have the second conductivity type,
wherein the first junction pattern is spaced apart from the impurity region,
wherein the second junction pattern contacts the impurity region.

2. The memory device of claim 1 , the memory device further comprising:
a contact plug on the first junction pattern and connected to the first junction pattern; and
an insulating dielectric pattern between the write gate and the top surface of the impurity region and between the read gate and the top surface of the semiconductor substrate.

3. The memory device of claim 2 , wherein the second junction pattern contacts the semiconductor substrate and the impurity region.

4. The memory device of claim 1 , the memory device further comprising a third junction pattern directly adjacent a second side of the write gate, wherein the third junction pattern contacts the impurity region.

5. The memory device of claim 1 , wherein the semiconductor substrate comprises active regions, each of the write gate and the read gate has a portion positioned between the active regions of the semiconductor substrate, and
wherein the portion of the write gate and the portion of the read gate face sidewalls of the active regions of the semiconductor substrate.

6. A memory device, comprising:
a semiconductor substrate having a first conductivity type;
an impurity region in the semiconductor substrate, wherein the impurity region has a second conductivity type that is different from the first conductivity type;
an insulating dielectric pattern on a top surface of the semiconductor substrate and on a top surface of the impurity region;
first and second read gates on the insulating dielectric pattern opposite the semiconductor substrate;
first and second write gates on the insulating dielectric pattern opposite the impurity region; and
a first junction pattern between the first write gate and the second write gate;
a second junction pattern between the first read gate and the second read gate; and
a contact plug disposed between the first read gate and the second read gate and connected to the second junction pattern,
wherein the first junction pattern has a bottom surface surrounded by the impurity region,
wherein the second junction pattern is spaced apart from the impurity region, and
wherein the first and second junction patterns have the second conductivity type.

7. The memory device of claim 6 , the memory device further comprising a third junction pattern between the first read gate and the first write gate,
wherein the third junction contacts the semiconductor substrate and the impurity region.

8. The memory device of claim 6 , the memory device further comprising
a bit line that crosses over the first write gate, the second write gate, the first read gate, and the second read gate and that is connected to the contact plug.

9. The memory device of claim 6 , wherein the semiconductor substrate comprises active regions,
wherein the first write gate, the second write gate, the first read gate, and the second read gate have portions that are positioned between the active regions of the semiconductor substrate respectively,
wherein the portions of the first write gate, the second write gate, the first read gate, and the second read gate face sidewalls of the active regions of the semiconductor substrate, respectively.

10. A memory device, comprising:
a semiconductor substrate having a first conductivity type;
an impurity region in a top region of the semiconductor substrate, wherein the impurity region has a second conductivity type that is different from the first conductivity type;
a read gate on a top surface of the semiconductor substrate;
a first write gate on a top surface of the impurity region;
a first junction pattern directly adjacent a first side of the first write gate;
a second junction pattern on a second side of the read gate, wherein the first junction pattern is adjacent a first side of the read gate; and
a bit line contact plug disposed on the second junction pattern and connected to the second junction pattern;
wherein the first junction pattern contacts the impurity region,
wherein the first junction pattern has the second conductivity type, and
wherein the second junction pattern has the second conductivity type.

11. The memory device of claim 10 , wherein a bottom surface of the impurity region extends below a bottom surface of the first junction pattern, the memory device further including an insulating dielectric pattern between the first write gate and the top surface of the impurity region and between the read gate and the top surface of the semiconductor substrate.

12. The memory device of claim 10 , wherein the first junction pattern further contacts the semiconductor substrate.

13. The memory device of claim 12 , wherein the first junction pattern is disposed between the read gate and the first write gate, wherein the read gate and the first write gate are adjacent each other.

14. The memory device of claim 10 , wherein the first junction pattern has a bottom surface that is surrounded by the impurity region,
the memory device further comprising a second write gate on the top surface of the impurity region, wherein the first write gate and the second write gate are adjacent each other,
wherein the first junction pattern is between the first write gate and the second write gate.

15. The memory device of claim 14 , the read gate comprises a first read gate,
the memory device further comprising
a second read gate on the top surface of the semiconductor substrate;
wherein the second junction pattern is between the first read gate and the second read gate, and
wherein the second junction pattern contacts the semiconductor substrate.

16. The memory device of claim 10 , the memory device further comprising
a third junction pattern directly adjacent a second side of the first write gate,
wherein the third junction pattern has a bottom surface that is surrounded by the impurity region.

17. The memory device of claim 16 , the memory device further comprising:
a second write gate on the top surface of the impurity region; and
a fourth junction pattern directly adjacent a first side of the second write gate,
wherein the third junction pattern is directly adjacent a second side of the second write gate, and
wherein the fourth junction pattern contacts the semiconductor substrate and the impurity region.

18. The memory device of claim 10 , wherein the semiconductor substrate comprises active regions,
wherein the first write gate has a vertically extended portion positioned between active regions of the semiconductor substrate,
wherein the read gate has a vertically extended portion positioned between the active regions of the semiconductor substrate, and
wherein the vertically extended portion of the read gate and the vertically extended por

Assignees

• Choi Hyun Min
• Pae Sangwoo
• Cho Hagju
• Samsung Electronics Co Ltd

Inventors

• Choi Hyun-Min
• Pae Sangwoo
• Cho Hagju

Classifications

• G11C17/08

  using semiconductor devices, e.g. bipolar elements (G11C17/06, G11C17/14 take precedence) · CPC title

• H01L27/1126 Primary

  Electricity · mapped topic

• H10B41/00 Primary

  Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates · CPC title

• H10B20/383 Primary

  Channel doping programmed · CPC title