Integrated assemblies and methods of forming integrated assemblies

Patent metadata

Field	Value
Publication number	US-10998326-B2
Application number	US-202016907858-A
Country	US
Kind code	B2
Filing date	Jun 22, 2020
Priority date	Nov 23, 2015
Publication date	May 4, 2021
Grant date	May 4, 2021

Abstract

Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

First claim

We claim:

1. A method of forming an integrated assembly, comprising:
forming a stack of materials over a substrate, the stack comprising a first tier over the substrate, an etch stop material over the first tier, a second tier over and directly against the etch stop material, a replaceable material over and directly against the second tier, and a third tier over the replaceable material;
forming first and second substantially vertical semiconductor channel structures extending through the stack of materials;
doping the first and second substantially vertical semiconductor channel structures to form channel regions having a more-heavily-doped region interfacing a less-heavily-doped region at a boundary region; and
replacing the replaceable material with a conductive material to form a gating structure between the first and second substantially vertical semiconductor channel structures, the gating structure having a first gating region extending substantially vertically along the first substantially vertical semiconductor channel structure, having a second gating region extending substantially vertically along the second substantially vertical semiconductor channel structure, and having an interconnecting region extending horizontally between the first and second gating regions, the interconnecting region being vertically narrower than a vertical length of the first and second gating regions.

2. The method of claim 1 wherein the first and second substantially vertical semiconductor channel structures have laterally extending portions over an uppermost surface of the first and second gating regions, respectively.

3. The method of claim 1 wherein forming the first and second substantially vertical semiconductor channel structures retains a region of the etch stop material that is present in a final integrated assembly.

4. The method of claim 1 wherein the first gating region is formed to extend along a segment of the more-heavily-doped region, along a segment of the less-heavily-doped region, and along the boundary region of the first substantially vertical semiconductor channel structure.

5. The method of claim 1 wherein the more-heavily doped region and the less-heavily doped region are majority doped to have the same majority carriers.

6. A method of forming an integrated assembly, comprising:
forming a stack of materials over a substrate, the stack comprising a first tier over the substrate, an etch stop material over the first tier, a second tier over the etch stop material, a replaceable material over the second tier, and a third tier over the replaceable material;
forming first and second substantially vertical semiconductor channel structures extending through the stack of materials;
doping the first and second semiconductor substantially vertical channel structures to form channel regions having a more-heavily-doped region interfacing a less-heavily-doped region at a boundary region; and
replacing the replaceable material with a conductive material to form a gating structure between the first and second substantially vertical semiconductor channel structures, the gating structure and having a first gating region extending substantially vertically along the first substantially vertical semiconductor channel structure, having a second gating region extending substantially vertically along the second substantially vertical semiconductor channel structure, and having an interconnecting region extending horizontally between the first and second gating regions, the interconnecting region being vertically narrower than a vertical length of the first and second gating regions, wherein the first and second substantially vertical semiconductor channel structures have laterally extending portions over an uppermost surface of the first and second gating regions, respectively;
forming an etch resistant material over the laterally extending portions, the etch resistant material extending an entirety of a distance between and across the first and second substantially vertical semiconductor channel structures;
forming an insulative material over the etch resistant material;
forming a first opening through the insulative material and the etch resistant material over the first substantially vertical semiconductor channel structure;
forming a second opening through the insulative material and the etch resistant material over the second substantially vertical semiconductor channel structure; and
providing a conductive material within the first and second openings.

7. The method of claim 6 wherein the conductive material is formed in direct physical contact with the laterally extending portions of the first and second substantially vertical semiconductor channel structures.

8. The method of claim 6 wherein the forming the first and second openings retains a region of the etch-resistant material that is present in a final integrated assembly.

Assignees

• Micron Technology Inc

Inventors

• Dorhout Justin B
• Parekh Kunal R
• Roberts Martin C
• Akhtar Mohd Kamran
• Carter Chet E
• Daycock David

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P72/0418

  for etching · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P32/302

  Doping polycrystalline silicon or amorphous silicon layers · CPC title