Method of forming a complementary metal oxide semiconductor structure with N-type and P-type field effect transistors having symmetric source/drain junctions and optional dual silicides

Patent metadata

Field	Value
Publication number	US-9548306-B2
Application number	US-201615144924-A
Country	US
Kind code	B2
Filing date	May 3, 2016
Priority date	Feb 5, 2015
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

In a method of forming a semiconductor structure, different sections of a dielectric layer are etched at different stages during processing to form a first gate sidewall spacer for a first FET (e.g., a NFET) and a second gate sidewall spacer for a second FET (e.g., a PFET) such that the first and second gate sidewall spacers are symmetric. Raised source/drain regions for the first FET are formed immediately following first gate sidewall spacer formation and raised source/drain regions for the second FET are formed immediately following second gate sidewall spacer formation. Since the gate sidewall spacers of the two FETs are symmetric, the source/drain junctions of the two FETs will also be symmetric. Additionally, due to an etch stop layer formed on the raised source/drain regions of the first FET, but not the second FET, different metal silicides on the raised source/drain regions of the different FETs.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a substrate;
a first transistor above said substrate and comprising:
a first semiconductor body comprising first source/drain regions and a first channel region between said first source/drain regions;
a first gate structure adjacent to said first channel region;
first raised source/drain regions on said first source/drain regions; and,
a first gate sidewall spacer between said first raised source/drain regions and said first gate structure;

a second transistor above said substrate and comprising:
a second semiconductor body comprising second source/drain regions and a second channel region between said first source/drain regions;
a second gate structure adjacent to said second channel region;
second raised source/drain regions on said second source/drain regions; and,
a second gate sidewall spacer between said second raised source/drain regions and said second gate structure, said first gate sidewall spacer and said second gate sidewall spacer being discrete portions of a first dielectric layer;

a second dielectric layer above said first transistor immediately adjacent to said first raised source/drain regions;
a third dielectric layer on said second dielectric layer; and,
a fourth dielectric layer on said third dielectric layer and further extending laterally over said second transistor so as to be immediately adjacent to said second raised source/drain regions.

2. The semiconductor structure of claim 1 , said first gate sidewall spacer and said second gate sidewall spacer having approximately equal thicknesses and said first raised source/drain regions being separated from said first channel region and said second raised source/drain regions being separated from said second channel region by approximately equal distances.

3. The semiconductor structure of claim 1 ,
said first raised source/drain regions comprising a first epitaxial silicon layer in situ doped with a first dopant, and
said second raised source/drain regions comprising a second epitaxial silicon layer in situ doped with a second dopant that is different from said first dopant.

4. The semiconductor structure of claim 1 , said second dielectric layer comprising a different dielectric material than said first dielectric layer, said third dielectric layer and said fourth dielectric layer.

5. The semiconductor structure of claim 1 , said first dielectric layer, said third dielectric layer and said fourth dielectric layer comprising nitride layers and said second dielectric layer comprising an oxide layer.

6. The semiconductor structure of claim 1 , further comprising first contacts and second contacts,
said second contacts extending through said fourth dielectric layer to metal silicide layers on said second raised source/drain regions,
said first contacts extending through said fourth dielectric layer, said third dielectric layer and said second dielectric layer to additional metal silicide layers on said first raised source/drain regions, said metal silicide layers and said additional metal silicide layers comprising different metal silicides.

7. The semiconductor structure of claim 6 , said first contacts and said second contacts each comprising a metal liner immediately adjacent to said metal silicide layers and said additional metal silicide layers.

8. The semiconductor structure of claim 7 , said metal silicide layers, said additional metal silicide layers and said metal liner comprising different metals.

9. The semiconductor structure of claim 7 ,
said metal silicide layers and said additional metal silicide layers comprising different metals, and
said additional metal silicide layers and said metal liner comprising a same metal.

10. A semiconductor structure comprising:
a substrate;
a first transistor above said substrate and comprising:
a first semiconductor body comprising first source/drain regions and a first channel region between said first source/drain regions;
a first gate structure adjacent to said first channel region;
first raised source/drain regions on said first source/drain regions; and,
a first gate sidewall spacer between said first raised source/drain regions and said first gate structure;

a second transistor above said substrate and comprising:
a second semiconductor body comprising second source/drain regions and a second channel region between said first source/drain regions;
a second gate structure adjacent to said second channel region;
second raised source/drain regions on said second source/drain regions; and,
a second gate sidewall spacer between said second raised source/drain regions and said second gate structure, said first gate sidewall spacer and said second gate sidewall spacer being discrete portions of a first dielectric layer;

a second dielectric layer above said first transistor immediately adjacent to said first raised source/drain regions;
a third dielectric layer on said second dielectric layer;
a fourth dielectric layer on said third dielectric layer and further extending laterally over said second transistor so as to be immediately adjacent to said second raised source/drain regions; and
first contacts and second contacts,
said second contacts extending through said fourth dielectric layer to metal silicide layers on said second raised source/drain regions,
said first contacts extending through said fourth dielectric layer, said third dielectric layer and said second dielectric layer to additional metal silicide layers on said first raised source/drain regions, said metal silicide layers and said additional metal silicide layers comprising different metal silicides.

11. The semiconductor structure of claim 10 , said first gate sidewall spacer and said second gate sidewall spacer having approximately equal thicknesses and said first raised source/drain regions being separated from said first channel region and said second raised source/drain regions being separated from said second channel region by approximately equal distances.

12. The semiconductor structure of claim 10 ,
said first raised source/drain regions comprising a first epitaxial silicon layer in situ doped with a first dopant, and
said second raised source/drain regions comprising a second epitaxial silicon layer in situ doped with a second dopant that is different from said first dopant.

13. The semiconductor structure of claim 10 , said second dielectric layer comprising a different dielectric material than said first dielectric layer, said third dielectric layer and said fourth dielectric layer.

14. The semiconductor structure of claim 10 , said first dielectric layer, said third dielectric layer and said fourth dielectric layer comprising nitride layers and said second dielectric layer comprising an oxide layer.

15. The semiconductor structure of claim 10 , said first contacts and said second contacts each comprising a metal liner immediately adjacent to said metal silicide layers and said additional metal silicide layers.

16. The semiconductor structure of claim 15 , said metal silicide layers, said additional metal silicide layers and said metal liner comprising different metals.

17. The semiconductor structure of claim 15 ,
said additional metal silicide layers and said metal liner comprising a same metal.

18. A semiconductor structure comprising:
a substrate;
a N-type transistor above said substrate and comprising:
a first semiconductor body comprising first source/drain regions and a first channel region between said first source/drain regions;
a f

Assignees

• Globalfoundries Inc

Inventors

• Basker Veeraraghavan S
• Bryant Andres
• Yamashita Tenko

Classifications

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H01L27/0922

  Electricity · mapped topic

• H01L21/8238

  Electricity · mapped topic

• H01L29/0847

  Electricity · mapped topic