Magnetoelectric random access memory array and methods of operating the same

Patent metadata

Field	Value
Publication number	US-10354710-B2
Application number	US-201715728840-A
Country	US
Kind code	B2
Filing date	Oct 10, 2017
Priority date	Jul 24, 2017
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

A memory cell includes a VCMA magnetoelectric memory element and a two-terminal selector element connected in series to the magnetoelectric memory element.

First claim

What is claimed is:

1. A memory cell, comprising:
a VCMA magnetoelectric memory element; and
a two-terminal selector element connected in series to the magnetoelectric memory element;
wherein:
the magnetoelectric memory element comprises a magnetoelectric tunnel junction comprising a ferromagnetic reference layer, a ferromagnetic free layer and an insulating tunneling oxide layer located between the reference layer and the free layer;
the memory cell is configured to be written into a set state by application of a first voltage pulse of a first polarity, and to be written into a reset state by application of a second voltage pulse of the first polarity;
the memory cell is configured to be read by application of a third voltage of a second polarity opposite to the first polarity;
a magnetization of the free layer is configured to transition from a parallel state with respect to a magnetization of the reference layer to an antiparallel state by application of the first voltage pulse of the first polarity followed by an application of a stopping voltage pulse of the second polarity opposite to the first polarity and lower magnitude than the first voltage pulse; and
the magnetization of the free layer is configured to transition from the antiparallel state to the parallel state by application of the second voltage pulse of the first polarity followed by an application of a stopping voltage pulse of the first polarity and lower magnitude than the second voltage pulse.

2. The memory cell of claim 1 , wherein the two-terminal selector element has non-linear voltage-current characteristics in both polarities and exhibits hysteresis.

3. The memory cell of claim 2 , wherein the two-terminal selector element comprises a threshold selector element, the ferromagnetic reference layer comprises a first CoFeB layer, the ferromagnetic free layer comprises a second CoFeB layer, and the insulating tunneling oxide layer comprises an MgO layer.

4. The memory cell of claim 2 , wherein the two-terminal selector element comprises a volatile conductive bridge.

5. The memory cell of claim 2 , wherein the two-terminal selector element comprises a chalcogenide ovonic threshold switch.

6. A two-dimensional memory array comprising a plurality of bit lines and a plurality of word lines arranged in a cross point configuration, comprising a respective memory cell of claim 1 connected to a respective one of the plurality of bit lines and a respective one of the plurality of word lines at each intersection region of the two-dimensional memory array.

7. A memory cell, comprising:
a VCMA magnetoelectric memory element; and
a two-terminal selector element connected in series to the magnetoelectric memory element;
wherein:
the magnetoelectric memory element comprises a magnetoelectric tunnel junction comprising a ferromagnetic reference layer, a ferromagnetic free layer and an insulating tunneling oxide layer located between the reference layer and the free layer;
the memory cell is configured to be written into a set state by application of a first voltage pulse of a first polarity, and to be written into a reset state by application of a second voltage pulse of the first polarity;
the memory cell is configured to be read by application of a third voltage of a second polarity opposite to the first polarity;
a magnetization of the free layer is configured to transition from a parallel state with respect to a magnetization of the reference layer to an antiparallel state by application of the first voltage pulse of the first polarity, followed by a zero bias period, and followed by an application of a stopping voltage pulse of the second polarity opposite to the first polarity and lower magnitude than the first voltage pulse; and
the magnetization of the free layer is configured to transition from the antiparallel state to the parallel state by application of the second voltage pulse of the first polarity, followed by the zero bias period, and followed by an application of a stopping voltage pulse of the first polarity and lower magnitude than the second voltage pulse.

8. The memory cell of claim 7 , wherein the two-terminal selector element has non-linear voltage-current characteristics in both polarities and exhibits hysteresis.

9. The memory cell of claim 8 , wherein the two-terminal selector element comprises a threshold selector element, the ferromagnetic reference layer comprises a first CoFeB layer, the ferromagnetic free layer comprises a second CoFeB layer, and the insulating tunneling oxide layer comprises an MgO layer.

10. The memory cell of claim 8 , wherein the two-terminal selector element comprises a volatile conductive bridge.

11. The memory cell of claim 8 , wherein the two-terminal selector element comprises a chalcogenide ovonic threshold switch.

12. A two-dimensional memory array comprising a plurality of bit lines and a plurality of word lines arranged in a cross point configuration, comprising a respective memory cell of claim 7 connected to a respective one of the plurality of bit lines and a respective one of the plurality of word lines at each intersection region of the two-dimensional memory array.

Assignees

• Sandisk Technologies Llc

Inventors

• Petti Christopher
• Robertson Neil
• Bandyopadhyay Abhijit

Classifications

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C11/16

  using elements in which the storage effect is based on magnetic spin effect · CPC title

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C11/1659

  Cell access · CPC title

• G11C11/1655

  Bit-line or column circuits · CPC title