Selectively reducing graph based analysis pessimism

Patent metadata

Field	Value
Publication number	US-10354042-B2
Application number	US-201414480543-A
Country	US
Kind code	B2
Filing date	Sep 8, 2014
Priority date	Sep 8, 2014
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

A method, system or computer usable program product for improving a circuit design having a set of endpoint circuits including identifying a subset of the set of endpoint circuits for further timing analysis based on graph based analysis (GBA) of the circuit design; performing path based analysis (PBA) of a set of endpoint circuit paths in the subset of endpoint circuits; and providing a timing margin between graph based analysis and path based analysis for each of the set of endpoint circuit paths for reducing pessimism in subsequent graph based analysis of the set of endpoint circuit paths.

First claim

What is claimed is:

1. A computer-implemented method of designing an integrated circuit (IC) design, the computer-implemented method comprising:
identifying, by a processor, a set of endpoints of the IC design;
performing, by the processor, a first graph based analysis associated with the set of endpoints;
performing, by the processor, a path based analysis associated with the set of endpoints;
determining, by the processor, a timing margin between the graph based analysis and the path based analysis associated with each endpoint in the set of endpoints;
performing, by the processor, a second graph based analysis of each endpoint in the set of endpoints in accordance with the timing margin determined for the endpoint; and
modifying, by the processor, the IC design in accordance with the second graph based analysis.

2. The computer-implemented method of claim 1 further comprising implementing, by the processor, each timing margin as a timing exception.

3. The computer-implemented method of claim 1 wherein for each endpoint the timing margin is calculated as a difference between the graph based analysis and the path based analysis associated with the endpoint.

4. The computer-implemented method of claim 1 wherein each timing margin is stored as a timing exception to the corresponding endpoint circuit path.

5. The computer-implemented method of claim 1 further comprising identifying, by the processor, a minimum number of pins to uniquely identify each endpoint.

6. The computer-implemented method of claim 5 wherein each timing margin is stored as a timing exception to the corresponding endpoint circuit path using the identified minimum number of pins for that endpoint circuit path.

7. The method of computer-implemented claim 1 further comprising modifying, by the processor, circuit elements disposed in at least one of the paths associated with the endpoint and in accordance with the timing margin associated with the endpoint.

8. A non-transitory computer readable storage medium comprising instructions which when executed by a processor, causes the processor to:
identify a set of endpoints of an integrated circuit design;
perform a first graph based analysis associated with the set of endpoints;
perform path based analysis associated with the set of endpoints;
determine a timing margin between the graph based analysis and the path based analysis associated with each endpoint;
perform a second graph based analysis of each endpoint in the set of endpoints in accordance with the timing margin determined for the endpoint; and
modify the IC design in accordance with the second graph based analysis.

9. The non-transitory computer readable storage medium of claim 8 wherein said instructions further cause the processor to implement each timing margin as a timing exception.

10. The non-transitory computer readable storage medium of claim 8 wherein for each endpoint the timing margin is calculated as a difference between the graph based analysis and the path based analysis associated with the endpoint.

11. The non-transitory computer readable storage medium of claim 8 wherein each timing margin is stored as a timing exception to the corresponding endpoint circuit path.

12. The non-transitory computer readable storage medium of claim 8 wherein said instructions further cause the processor to identify a minimum number of pins to uniquely identify each endpoint circuit path.

13. The non-transitory computer readable storage medium of claim 12 wherein each timing margin is stored as a timing exception to the corresponding endpoint circuit path using the identified minimum number of pins for that endpoint circuit path.

14. The non-transitory computer readable storage medium of claim 8 wherein said instructions further cause the processor to modify circuit elements disposed in at least one of the paths associated with the endpoint and in accordance with the timing margin associated with the endpoint.

15. A data processing system for designing an integrated circuit (IC), the data processing system comprising:
a processor; and
a memory storing program instructions which when executed by the processor cause the processor to:
identify a set of endpoints of the integrated circuit design;
perform a first graph based analysis associated with the set of endpoints;
perform path based analysis associated with the set of endpoints;
determine a timing margin between the graph based analysis and the path based analysis associated with each endpoint;
perform a second graph based analysis of each endpoint in the set of endpoints in accordance with the timing margin determined for the endpoint; and
modify the IC design in accordance with the second graph based analysis.

16. The data processing system of claim 15 wherein said instructions further cause the processor to implement each timing margin as a timing exception.

17. The data processing system of claim 15 wherein for each endpoint the timing margin is calculated as a difference between the graph based analysis and the path based analysis associated with the endpoint.

18. The data processing system of claim 15 wherein each timing margin is stored as a timing exception to the corresponding endpoint circuit path.

19. The data processing system of claim 15 wherein said instructions further cause the processor to identify a minimum number of pins to uniquely identify each endpoint circuit path.

20. The data processing system of claim 19 wherein each timing margin is stored as a timing exception to the corresponding endpoint circuit path using the identified minimum number of pins for that endpoint circuit path.

21. The data processing system of claim 15 wherein said instructions further cause the processor to modify circuit elements disposed in at least one of the paths associated with the endpoint and in accordance with the timing margin associated with the endpoint.

Assignees

• Synopsys Inc

Inventors

• Shyamsukha Ritesh
• Feng Chunyang
• Radhakrishnan Shankar
• Craven Ted L

Classifications

• G06F30/367

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/3312

  Timing analysis · CPC title

• G06F30/30

  Circuit design · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title