Zone-SDID mapping scheme for TLB purges

Patent metadata

Field	Value
Publication number	US-10353828-B2
Application number	US-201715810218-A
Country	US
Kind code	B2
Filing date	Nov 13, 2017
Priority date	Jun 7, 2017
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

Embodiments include techniques for using a zone-SDID mapping for translation lookaside buffer (TLB) purges, the embodiments include receiving a zone purge request, including zone attribute information, and searching for matching zone attribute information in a zone register using the zone purge request. Embodiments also include computing, based at least in part on the search, a state descriptor identifier (SDID) vector for each matching zone of the zone register, and reading TLB entries referenced in the zone purge request. Embodiments include comparing an SDID of the TLB entry against an SDID specified in the SDID vector, and purging the TLB entries based on the comparison.

First claim

What is claimed is:

1. A computer-implemented method for using a zone-SDID mapping for translation lookaside buffer (TLB) purges, the computer-implemented method comprising:
receiving a zone purge request, including zone attribute information;
searching for matching zone attribute information in a zone register using the zone purge request;
computing, based at least in part on the searching, a state descriptor identifier (SDID) vector for each matching zone of the zone register;
reading a TLB entry referenced in the zone purge request;
comparing an SDID of the TLB entry against an SDID specified in the SDID vector; and
purging the TLB entry based on the comparison.

2. The computer-implemented method of claim 1 , wherein zone attribute information includes at least one of thread or guest attribute information.

3. The computer-implemented method of claim 1 , wherein the zone purge request includes at least one of an additional purge qualifier.

4. The computer-implemented method of claim 1 , wherein the TLB entry excludes storing zone information in a combined region and segment-table entry portion of the TLB.

5. The computer-implemented method of claim 1 , wherein the zone register is implemented as separate content addressable memories.

6. The computer-implemented method of claim 1 , wherein the comparison is based on matching SDIDs and at least one of an additional purge criterion.

7. The computer-implemented method of claim 1 , wherein the SDID identifies at least one of a logical processing unit or virtual processor.

Assignees

• IBM

Inventors

• Brandt Uwe
• Gaertner Ute
• Heller Lisa C
• Helms Markus
• Jacobi Christian
• Koehler Thomas
• Lehnert Frank
• Navarro Jennifer A

Classifications

• G06F12/121 Primary

  using replacement algorithms · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F2212/7205

  Cleaning, compaction, garbage collection, erase control · CPC title

• G06F12/1441

  for a range · CPC title

• G06F12/0864

  using pseudo-associative means, e.g. set-associative or hashing · CPC title