Zone-SDID mapping scheme for TLB purges

US10353827B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10353827-B2
Application numberUS-201715615857-A
CountryUS
Kind codeB2
Filing dateJun 7, 2017
Priority dateJun 7, 2017
Publication dateJul 16, 2019
Grant dateJul 16, 2019

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  1. Title

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  2. Abstract

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Abstract

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Embodiments include techniques for using a zone-SDID mapping for translation lookaside buffer (TLB) purges, the embodiments include receiving a zone purge request, including zone attribute information, and searching for matching zone attribute information in a zone register using the zone purge request. Embodiments also include computing, based at least in part on the search, a state descriptor identifier (SDID) vector for each matching zone of the zone register, and reading TLB entries referenced in the zone purge request. Embodiments include comparing an SDID of the TLB entry against an SDID specified in the SDID vector, and purging the TLB entries based on the comparison.

First claim

Opening claim text (preview).

What is claimed is: 1. A system for using a zone-SDID mapping for translation lookaside buffer (TLB) purges, the system comprising: a translation lookaside buffer including a zone register, a combined region and segment-table entries, and page table entries; a storage medium, the storage medium being coupled to a processor; the processor configured to: receive a zone purge request, including zone attribute information; search for matching zone attribute information in a zone register using the zone purge request; compute, based at least in part on the search, a state descriptor identifier (SDID) vector for each matching zone of the zone register; read a TLB entry referenced in the zone purge request; compare an SDID of the TLB entry against an SDID specified in the SDID vector; and purge the TLB entry based on the comparison. 2. The system of claim 1 , wherein the zone attribute information includes at least one of thread or guest attribute information. 3. The system of claim 1 , wherein the zone purge request includes is at least one of an additional purge. 4. The system of claim 1 , wherein the TLB entry excludes storing zone information in a combined region and segment-table entry portion of the TLB. 5. The system of claim 1 , wherein the zone register is implemented as separate content addressable memories. 6. The system of claim 1 , wherein the comparison is based on matching SDIDs and at least one of an additional purge criterion. 7. The system of claim 1 , wherein the SDID identifies at least one of a logical processing unit or virtual processor. 8. A computer program product for using a zone-SDID mapping for translation lookaside buffer (TLB) purges, the computer program product comprising: a computer readable storage medium having stored thereon first program instructions executable by a processor to cause the processor to: receive a zone purge request, including zone attribute information; search for matching zone attribute information in a zone register using the zone purge request; compute, based at least in part on the search, a state descriptor identifier (SDID) vector for each matching zone of the zone register; read a TLB entry referenced in the zone purge request; compare an SDID of the TLB entry against an SDID specified in the SDID vector; and purge the TLB entry based on the comparison. 9. The computer program product of claim 8 , wherein the zone attribute information includes at least one of thread or guest attribute information. 10. The computer program product of claim 8 , wherein the zone purge request includes is at least one of an additional purge qualifier. 11. The computer program product of claim 8 , wherein the TLB entry excludes storing zone information in a combined region and segment-table entry portion of the TLB. 12. The computer program product of claim 8 , wherein the comparison is based on matching SDIDs and at least one of an additional purge criterion. 13. The computer program product of claim 8 , wherein the SDID identifies at least one of a logical processing unit or virtual processor.

Assignees

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Classifications

  • G06F12/121Primary

    using replacement algorithms · CPC title

  • using pseudo-associative means, e.g. set-associative or hashing · CPC title

  • Invalidation · CPC title

  • for a range · CPC title

  • using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

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What does patent US10353827B2 cover?
Embodiments include techniques for using a zone-SDID mapping for translation lookaside buffer (TLB) purges, the embodiments include receiving a zone purge request, including zone attribute information, and searching for matching zone attribute information in a zone register using the zone purge request. Embodiments also include computing, based at least in part on the search, a state descriptor…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification G06F12/121. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jul 16 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).