Memory system and error correcting method of the same

Patent metadata

Field	Value
Publication number	US-10353770-B2
Application number	US-201715826808-A
Country	US
Kind code	B2
Filing date	Nov 30, 2017
Priority date	Dec 14, 2016
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

An error correcting method of a memory system includes: reading data and an error correction code from a plurality of memory chips; correcting an error of the data based on the error correction code; determining whether or not a miscorrection occurs in the correcting of the error of the data; designating one memory chip among the plurality of the memory chips as a chip-killed memory chip when a miscorrection occurs; re-correcting the error of the data based on the error correction code in consideration of the designated chip-killed memory chip; and re-determining whether a miscorrection occurs in the re-correcting of the error of the data.

First claim

What is claimed is:

1. An error correcting method of a memory system, comprising:
reading data, an error correction code, and a miscorrection detecting code from a plurality of memory chips;
correcting an error of the data based on the error correction code;
determining whether or not a miscorrection occurs in the correcting of the error of the data based on the miscorrection detecting code;
designating one memory chip among the plurality of the memory chips as a chip-killed memory chip when a miscorrection occurs;
re-correcting the error of the data based on the error correction code in consideration of the designated chip-killed memory chip; and
re-determining whether a miscorrection occurs in the re-correcting of the error of the data based on the miscorrection detecting code,
wherein when a miscorrection is detected in the re-determining of whether the miscorrection occurs or not, the memory chip that is designated as the chip-killed memory chip among the plurality of the memory chips is changed with another memory chip, and then the re-correcting of the error of the data and the re-determining of whether the miscorrection occurs are repeated.

2. The error correcting method of claim 1 , further comprising, when a miscorrection is not detected in the deciding of whether the miscorrection occurs or not, ending the error correcting process.

3. The error correcting method of claim 2 , further comprising, when a miscorrection is not detected in the re-determining of whether the miscorrection occurs or not, determining the memory chip, that is designated as the designated chip-killed memory chip, as a chip-killed memory chip, and ending an error correcting process.

4. The error correcting method of claim 1 , wherein the error correction code includes one of an error correction code of a Reed Solomon (RS) scheme, an error correction code of a Bose-Chaudhuri-Hocquenghem (BCH) scheme and an error correction code of a Turbo scheme.

5. The error correcting method of claim 1 , wherein the error correction code is a Reed Solomon (RS) scheme.

6. A memory system, comprising:
a plurality of memory chips suitable for storing data, an error correction code, and a miscorrection detecting code;
an error correction circuit suitable for reading the data and the error correction code from the plurality of the memory chips, and correcting an error of the data based on the error correction code; and
a miscorrection detecting circuit suitable for detecting whether a miscorrection occurs or not in the error correction circuit based on the miscorrection detecting code,
wherein when the miscorrection detecting circuit detects a miscorrection of the error correction circuit, the error correction circuit designates one memory chip among the plurality of the memory chips as a chip-killed memory chip and re-corrects the error of the data based on the error correction code in consideration of the designated chip-killed memory chip,
wherein the error correction circuit performs an error correcting operation repeatedly by changing the memory chip which is designated as the chip-killed memory chip with another memory chip among the plurality of the memory chips, until no miscorrection is detected.

7. The memory system of claim 6 , wherein the error correction code includes one of an error correction code of a Reed Solomon (RS) scheme, an error correction code of a Bose-Chaudhuri-Hocquenghem (BCH) scheme and an error correction code of a Turbo algorithm.

8. The memory system of claim 6 , wherein the error correction circuit designates a particular memory chip among the plurality of the memory chips as a chip-killed memory chip and, when no miscorrection is detected, decides the particular memory chip as a chip-killed memory chip.

9. The memory system of claim 6 , wherein the error correction circuit and the miscorrection detecting circuit are included in a memory controller, and
the plurality of the memory chips are included in a memory module.

10. The memory system of claim 6 , wherein the memory system is capable of correcting errors in a case that N random errors (where N is an integer equal to or greater than ‘1’) occur in the plurality of the memory chips and one memory chip among the plurality of the memory chips is a chip-killed memory chip.

11. The memory system of claim 10 , wherein the number of bits of the error correction code used in the memory system is less than the number of bits of the error correction code required to correct the errors in the case that N random errors (where N is an integer equal to or greater than ‘1’) occur in the plurality of the memory chips and one memory chip among the plurality of the memory chips is the chip-killed memory chip, without the memory system designating one memory chip among the plurality of the memory chips as a chip-killed memory chip.

Assignees

• Sk Hynix Inc

Inventors

• Lee Sung-Eun
• Kwon Jung-Hyun
• JO Sang-Gu

Classifications

• H03M13/15

  Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes (H03M13/17 takes precedence) · CPC title

• G11C29/02

  Detection or location of defective auxiliary circuits, e.g. defective refresh counters · CPC title

• H03M13/1515

  Reed-Solomon codes · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F11/1028 Primary

  Adjacent errors, e.g. error in n-bit (n>1) wide storage units, i.e. package error · CPC title