Managing execution of computer tasks under time constraints

Patent metadata

Field	Value
Publication number	US-10353766-B2
Application number	US-201615260402-A
Country	US
Kind code	B2
Filing date	Sep 9, 2016
Priority date	Sep 9, 2016
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

A computer-implemented method comprises identifying a computer task; determining a hardware exception source associated with the computer task; determining an exception unit associated with the hardware exception source; determining a parallelization factor associated with the hardware exception source; and determining a parallel execution scenario associated with the computer task based on the exception unit and the parallelization factor. A corresponding computer program product and computer system are also disclosed.

First claim

What is claimed is:

1. A computer-implemented method comprising:
identifying a computer task;
determining a computer task exception unit, with the determination of the computer task exception unit including:
receiving a computer exception data set, with the computer exception data set including information indicative of a given computer exception being associated with a given computer exception source, and
responsive to the receipt of the computer exception data set, modeling the portions of a first computer system affected by the given computer exception that is associated with the given computer exception source;

determining a parallelization factor, based, at least in part, upon the modeled portions of the first computer system;
allocating a quantity N computer task exception units to parallel perform the computer task; and
performing the computer task in parallel on the N computer task exception units.

2. The computer-implemented method of claim 1 , wherein:
the modeled portions of the first computer system includes information indicative of the portions of the first computer system that are yet to be determined to be impacted by a computer exception source;
the historical computer task error data includes an instance of an operating system failure; and
the computer task exception unit is a computer system.

3. The computer-implemented method of claim 1 , wherein:
the historical computer task error data includes an instance of a network failure; and
the computer task exception unit is a computer network system.

4. The computer-implemented method of claim 1 , wherein:
the historical computer task error data includes an instance of a file system failure.

5. The computer-implemented method of claim 1 , wherein:
the historical computer task error data includes an instance of a storage failure; and
the computer task exception unit is a computer storage system.

6. The computer-implemented method of claim 1 , further comprising:
determining an exception impact indicator that reflects the impact that an occurrence of an exception in a computer task exception unit has on performing the computer task in a timely manner.

7. The computer-implemented method of claim 1 , further comprising:
determining an exception occurrence frequency indicator;

wherein the parallelization factor is determined based on the exception occurrence frequency indicator.

8. A computer program product comprising:
a non-transitory machine readable storage device; and
computer code stored on the non-transitory machine readable storage device, with the computer code including instructions for causing a processor(s) set to perform operations including the following:
identifying a computer task,
determining a computer task exception unit, with the determination of the computer task exception unit including:
receiving a computer exception data set, with the computer exception data set including information indicative of a given computer exception being associated with a given computer exception source, and
responsive to the receipt of the computer exception data set, modeling the portions of a first computer system affected by the given computer exception that is associated with the given computer exception source,

determining a parallelization factor, based, at least in part, upon the modeled portions of the first computer system,
allocating a quantity N computer task exception units to parallel perform the computer task, and
performing the computer task in parallel on the N computer task exception units.

9. The computer program product of claim 8 , wherein:
the modeled portions of the first computer system includes information indicative of the portions of the first computer system that are yet to be determined to be impacted by a computer exception source;
the historical computer task error data includes an instance of an operating system failure; and
the computer task exception unit is a computer system.

10. The computer program product of claim 8 , wherein:
the historical computer task error data includes an instance of a network failure; and
the computer task exception unit is a computer network system.

11. The computer program product of claim 8 , wherein:
the historical computer task error data includes an instance of a file system failure.

12. The computer program product of claim 8 , wherein:
the historical computer task error data includes an instance of a storage failure; and
the computer task exception unit is a computer storage system.

13. The computer program product of claim 8 , wherein the computer code further includes instructions for causing the processor(s) set to perform the following operations:
determining an exception impact indicator that reflects the impact that an occurrence of an exception in a computer task exception unit has on performing the computer task in a timely manner.

14. The computer program product of claim 8 , wherein the computer code further includes instructions for causing the processor(s) set to perform the following operations:
determining an exception occurrence frequency indicator;
wherein the parallelization factor is determined based on the exception occurrence frequency indicator.

15. A computer system comprising:
a processor(s) set;
a machine readable storage device; and
computer code stored on the machine readable storage device, with the computer code including instructions for causing the processor(s) set to perform operations including the following:
identify a computer task,
determining a computer task exception unit, with the determination of the computer task exception unit including:
receiving a computer exception data set, with the computer exception data set including information indicative of a given computer exception being associated with a given computer exception source, and
responsive to the receipt of the computer exception data set, modeling the portions of a first computer system affected by the given computer exception that is associated with the given computer exception source,
determining a parallelization factor, based, at least in part, upon the modeled portions of the first computer system,
allocating a quantity N computer task exception units to parallel perform the computer task, and
performing the computer task in parallel on the N computer task exception units.

16. The computer system of claim 15 , wherein:
the modeled portions of the first computer system includes information indicative of the portions of the first computer system that are yet to be determined to be impacted by a computer exception source;
the historical computer task error data includes an instance of an operating system failure; and
the computer task exception unit is a computer system.

17. The computer system of claim 15 , wherein:
the historical computer task error data includes an instance of a network failure; and
the computer task exception unit is a computer network system.

18. The computer system of claim 15 , wherein:
the historical computer task error data includes an instance of a file system failure.

19. The computer system of claim 15 , wherein:
the historical computer task error data includes an instance of a storage failure; and
the computer task exception unit is a computer storage system.

20. The computer system of claim 15 , wherein the computer code further includes instructions for causing the processor(s) set to perform the following operations:
determining an exception impac

Assignees

• IBM

Inventors

• Ding Zhaohui
• Huang Kai
• Jiang jun hua
• Xu Da
• Zhu Bo

Classifications

• G06F2209/481

  Exception handling · CPC title

• G06F11/079

  Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36) · CPC title

• G06F2209/506

  Constraint · CPC title

• G06F9/52

  Program synchronisation; Mutual exclusion, e.g. by means of semaphores · CPC title

• G06F11/0793 Primary

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title