Operating System-Managed Interrupt Steering in Multiprocessor Systems

Patent metadata

Field	Value
Publication number	US-2016357689-A1
Application number	US-201615241104-A
Country	US
Kind code	A1
Filing date	Aug 19, 2016
Priority date	Jun 13, 2013
Publication date	Dec 8, 2016
Grant date	—

Abstract

An operating system includes an interrupt router that dynamically steers each interrupt to one or more processors within set of processors based on overall load information from the set of processors. An interrupt source is assigned to a processor based on the load imposed by the interrupt source and the target overall load for the processor. For example, each processor can maintain information about each interrupt it processes over time. The operating system receives this historical load information to determine an expected load for interrupts of a given type from a given device, an overall load on the system, and a target load for each processor. Given a set of interrupt sources, their expected loads, and target load for each processor, each interrupt source can be assigned dynamically to a processor during runtime of the system. These assignments can be changed given current operating conditions of the system.

First claim

What is claimed is:

1 . A computer-implemented process performed by a computer including a plurality of processors, comprising:
an interrupt router assigning each interrupt source of a plurality of interrupt sources to a selected processor from among the plurality of processors, the plurality of interrupt sources having a corresponding plurality of interrupt handlers; in response to each interrupt from an interrupt source of the plurality of interrupt sources, executing the interrupt handler for the interrupt source on the processor assigned to the interrupt source; each interrupt handler storing, in a first data structure in a memory for the processor executing the interrupt handler, data indicating an amount of processing time consumed due to executing the interrupt handler; the interrupt router receiving from the plurality of processors, into a second data structure in a memory for the interrupt router, the data indicating the amount of processing time consumed by the plurality of processors due to executing the interrupt handlers; the interrupt router determining a load on the computer due to interrupt handling by the plurality of processors based on at least the received data; and the interrupt router reassigning the plurality of interrupt sources among the plurality of processors based on at least a function of the determined load so as to distribute the load among the processors while maximizing a number of processors that are idle.

2 . The computer-implemented process of claim 1 , further comprising, in response to executing the interrupt handler for an interrupt:
any process invoked by the interrupt handler further storing, in the first data structure in the memory for the processor executing the invoked process, data indicating an amount of processing time consumed by the invoked process; wherein the interrupt router further stores, in the second data structure, the data indicating the amount of processing time consumed by any processes invoked by the interrupt handlers.

3 . The computer-implemented process of claim 1 , wherein reassigning comprises:
the interrupt router identifying a number of processors, from among the plurality of processors, available for processing interrupts; the interrupt router selecting a number of processors, from among the identified number of processors available for processing interrupts, such that the number of selected processors matches the determined load divided by a target per-processor load.

4 . The computer-implemented process of claim 1 , further comprising:
the interrupt router aggregating, by interrupt source, the data received from the plurality of processors.

5 . The computer-implemented process of claim 4 , further comprising determining the amount of processing time by:
storing a system time stamp when beginning execution of the interrupt handler; computing a difference between a system time stamp observed when ending execution of the interrupt handler; and storing the computed difference.

6 . The computer-implemented process of claim 5 , wherein determining the amount of processing time further comprises:
for any process invoked by the interrupt handler, storing a system time stamp when beginning execution of the process; computing a difference between a system time stamp observed when ending execution of the process; and storing data indicative of the computed difference for the process and the computed difference for the interrupt handler.

7 . The computer-implemented process of claim 6 , wherein determining the amount of processing time further comprises:
for any preemptive activity preempting interrupt processing by the interrupt handler and associated processes, computing a difference between system time stamps observed when pausing the preempted interrupt processing and when restarting the preempted interrupt processing to have an amount of time for executing the preemptive activity; and wherein the computed difference for the interrupt handler excludes the amount of time for executing the preemptive activity.

8 . An article of manufacture comprising:
a computer storage medium comprising at least a memory or a storage device; computer program instructions stored on the computer storage medium which, when read from storage and processed by a processing device including a plurality of processors, instruct the processing device to perform a process comprising: assigning, by an interrupt router, each interrupt source of a plurality of interrupt sources to a selected processor from among the plurality of processors, the plurality of interrupt sources having a corresponding plurality of interrupt handlers; in response to each interrupt from an interrupt source of the plurality of interrupt sources, executing the interrupt handler for the interrupt source on the processor assigned to the interrupt source; storing, by each interrupt handler, in a first data structure in memory for the processor executing the interrupt handler, data indicating an amount of processing time consumed by the processor due to executing the interrupt handler; the interrupt router receiving, from the plurality of processors, into a second data structure in a memory for the interrupt router, the data indicating the amount of processing time consumed due to executing the interrupt handlers; the interrupt router determining a load on the processing device due to interrupt handling by the plurality of processors based on at least the received data; and the interrupt router reassigning the plurality of interrupt sources among the plurality of processors based on at least a function of the determined load so as to distribute the load among the processors while maximizing a number of processors that are idle.

9 . The article of manufacture of claim 8 , wherein the process further comprises, in response to executing the interrupt handler for an interrupt:
any process invoked by the interrupt handler further storing, in the first data structure in the memory for the processor executing the invoked process, data indicating an amount of processing time consumed by the invoked process; wherein the interrupt router further stores, in the second data structure, the data indicating the amount of processing time consumed by any processes invoked by the interrupt handlers.

10 . The article of manufacture of claim 8 , wherein reassigning comprises:
the interrupt router identifying a number of processors, from among the plurality of processors, available for processing interrupts; the interrupt router selecting a number of processors, from among the identified number of processors available for processing interrupts, such that the number of selected processors matches the determined load divided by a target per-processor load.

11 . The article of manufacture of claim 8 , wherein the process further comprises:
the interrupt router aggregating, by interrupt source, the data received from the plurality of processors.

12 . The article of manufacture of claim 11 , further comprising determining the amount of processing time by:
storing a system time stamp when beginning execution of the interrupt handler; computing a difference between a system time stamp observed when ending execution of the interrupt handler; and storing the computed difference.

13 . The article of manufacture of claim 12 , wherein determining the amount of processing time further comprises:
for any process invoked by the interrupt handler, storing a system time stamp when beginning execution of the process; computing a difference between a system time stamp observed when ending execution of the proc

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Raffman Andrew
• Kim Minsang
• Wohlgemuth Jason
• Brown Tristan
• Barakat Youssef
• Fatemieh Omid

Classifications

• G06F11/3024

  where the computing system component is a central processing unit [CPU] · CPC title

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F9/5083

  Techniques for rebalancing the load in a distributed system · CPC title

• G06F11/3419

  by assessing time · CPC title

• G06F2201/835

  Timestamp · CPC title