System converter that implements a run ahead run time guest instruction conversion/decoding process and a prefetching process where guest code is pre-fetched from the target of guest branches in an instruction sequence

Patent metadata

Field	Value
Publication number	US-10353680-B2
Application number	US-201514807353-A
Country	US
Kind code	B2
Filing date	Jul 23, 2015
Priority date	Jul 25, 2014
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

A system for an agnostic runtime architecture. The system includes a system emulation/virtualization converter, an application code converter, and a converter wherein a system emulation/virtualization converter and an application code converter implement a system emulation process, and wherein the system converter implements a system and application conversion process for executing code from a guest image, wherein the system converter or the system emulator. The system further includes a run ahead run time guest such an conversion/decoding process, and a prefetching process where guest code is pre-fetched from the target of guest branches in an instruction sequence.

First claim

What is claimed is:

1. A system comprising:
a processor;
a system emulation/virtualization converter;
an application code converter, wherein the system emulation/virtualization converter and the application code converter implement a system emulation process; and
a system converter, wherein the system converter implements a system and application conversion process for executing code from a guest image, wherein the code from the guest image comprises a first guest branch and a second guest branch, and wherein the system emulation process or the system and application conversion process are operable to implement:
a run ahead run time guest fetch and conversion/decoding process, wherein the run ahead run time guest fetch and conversion/decoding process converts the first guest branch into a first native branch and converts the second guest branch into a second native branch;
a prefetching process, wherein the code from the guest image is pre-fetched from corresponding targets of the first and second guest branches in an instruction sequence, and wherein the first guest branch and the second guest branch are pre-fetched into a guest fetch buffer; and
a frequency tracking process, wherein the frequency tracking process identifies the most frequently executed guest instructions of the code from the guest image.

2. The system of claim 1 , wherein the most frequently executed guest instructions and their mappings are stored at a low level cache structure.

3. The system of claim 1 , wherein a mapping table is used to provide an equivalent instruction format for a looked up guest instruction format.

4. The system of claim 1 , wherein the code from the guest image comprises application code and operating system/system specific code for execution.

5. The system of claim 1 , further comprising a plurality of conversion tables including a first level conversion table and a second level conversion table coupled to the guest fetch buffer converting the code from the guest image into corresponding native code.

6. A microprocessor comprising:
a system emulation/virtualization converter;
an application code converter, wherein the system emulation/virtualization converter and the application code converter implement a system emulation process; and
a system converter, wherein the system converter implements a system and application conversion process for executing code from a guest image, wherein the code from the guest image comprises a first guest branch and a second guest branch, and wherein the system and emulation process or the system and application conversion process are operable to implement:
a run ahead run time guest fetch and conversion/decoding process, wherein the run ahead run time guest fetch and conversion/decoding process converts the first guest branch into a first native branch and converts the second guest branch into a second native branch:
a prefetching process, wherein the code from the guest image is pre-fetched from corresponding targets of the first and second guest branches in an instruction sequence, and wherein the first guest branch and the second guest branch are pre-fetched into a guest fetch buffer; and
a frequency tracking process, wherein the frequency tracking process identifies the most frequently executed guest instructions of the code from the guest image.

7. The microprocessor claim 6 , wherein most frequently executed guest instructions and their mappings are stored at a low level cache structure.

8. The microprocessor of claim 6 , wherein a mapping table is used to provide an equivalent instruction format for a looked up guest instruction format.

9. The microprocessor of claim 6 , wherein the code from the guest image comprises application code and operating system/system specific code for execution.

10. The microprocessor of claim 6 , further comprising a plurality of conversion tables including a first level conversion table and a second level conversion table coupled to the guest fetch buffer for converting the code from the guest image into corresponding native code.

11. A computer system, comprising a microprocessor comprising a core and a plurality of caches, wherein the microprocessor further comprises:
a system emulation/virtualization converter;
an application code converter, wherein the system emulation/virtualization converter and the application code converter implement a system emulation process; and
a system converter, wherein the system converter implements a system and application conversion process for executing code from a guest image, wherein the code from the guest image comprises a first guest branch and a second guest branch, and wherein the system emulation process or the system and application conversion process are operable to implement:
a run ahead run time guest fetch and conversion/decoding process, wherein the run ahead run time guest fetch and conversion/decoding process converts the first guest branch into a first native branch and converts the second guest branch into a second native branch;
a prefetching process, wherein the code from the guest image is pre-fetched from corresponding targets of the first and second guest branches in an instruction sequence, and wherein the first guest branch and the second guest branch are pre-fetched into a guest fetch buffer; and
a frequency tracking process, wherein the frequency tracking process identifies the most frequently executed guest instructions of the code from the guest image.

12. The computer system of claim 11 , wherein most frequently executed guest instructions and their mappings are stored at a low level cache structure.

13. The computer system of claim 11 , wherein a mapping table is used to provide an equivalent instruction format for a looked up guest instruction format.

14. The computer system of claim 11 , further including a plurality of conversion tables including a first level conversion table and a second level conversion table coupled to the guest fetch buffer for converting the code from the guest image into corresponding native code.

Assignees

• Intel Corp

Inventors

• Abdallah Mohammad

Classifications

• G06F9/4552

  Involving translation to a different instruction set architecture, e.g. just-in-time translation in a JVM · CPC title

• G06F9/45516 Primary

  Runtime code conversion or optimisation · CPC title

• G06F9/45504

  Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators · CPC title

• G06F9/3804

  for branches, e.g. hedging, branch folding · CPC title

• G06F8/443 Primary

  Optimisation · CPC title