Resistive random access memory based multiplexers and field programmable gate arrays

Patent metadata

Field	Value
Publication number	US-10348306-B2
Application number	US-201815916566-A
Country	US
Kind code	B2
Filing date	Mar 9, 2018
Priority date	Mar 9, 2017
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

Resistive random access memory (RRAM) based multiplexers and field programmable gate arrays (FPGAs) are provided. The RRAM-based multiplexers and FPGAs include a 4T1R programming structure to program the RRAMs. The programming structure includes two programming transistors connected between the power supply and the top electrode of the RRAM and two programming transistors connected between the power supply and the bottom electrode of the RRAM. The programming transistors are used to set and rest the RRAMs. In the RRAM-based multiplexer programming transistors connected to the bottom electrodes are shared between a plurality of RRAMs. The shared programming transistors and an output inverter of the RRAM are provided in a deep N-well of the RRAM-based multiplexer. The programming transistors connected to the top electrodes of the RRAMs and a plurality of input inverters are provided in a regular well of the RRAM-based multiplexer.

First claim

What is claimed is:

1. A multiplexing structure comprising:
a plurality of resistive random access memories;
a plurality of multiplexer inputs coupled to a plurality of top electrodes of the plurality of resistive random access memories;
a multiplexer output coupled to a plurality of bottom electrodes of the plurality of resistive random access memories;
a plurality of first driving elements coupled to the plurality of top electrodes; and
a second driving element coupled to the plurality of bottom electrodes, wherein the second driving element is provided in a deep N-well of the multiplexor,
wherein the plurality of first driving elements and the second driving element program the plurality of resistive random access memories;
a first voltage domain providing a power supply to the plurality of first driving elements; and
a second voltage supply providing a power supply to the second driving element, wherein the first voltage domain is one of a constant voltage domain and a switchable voltage supply and wherein the second voltage domain is the other of the constant voltage domain and the switchable voltage supply,
wherein to set a resistive random access memory from the plurality of resistive random access memories, the switchable voltage supply provides a setting voltage to the second driving element, and
wherein to reset the resistive random access memory from the plurality of resistive random access memories, the switchable voltage supply provides a resetting voltage, different from the setting voltage, to the second driving element,
the second driving element including
a first transistor connected between a first positive supply of the second voltage domain and the plurality of bottom electrodes; and
a second transistor connected between a first negative supply of the second voltage domain and the plurality of bottom electrodes,

wherein the first voltage domain is the constant voltage domain and provides a voltage of VDD at a second positive supply connected to the plurality of first driving elements and 0V at a second negative supply connected to the plurality of first driving elements, and
wherein providing the setting voltage includes providing −Vprog+2VDD at the first positive supply and providing −Vprog+VDD at the first negative supply.

2. The multiplexing structure of claim 1 , further comprising:
a plurality of multiplexer input inverters provided between the plurality of multiplexer inputs and the plurality of top electrodes, wherein the first voltage domain provides the power supply to the plurality of multiplexer input inverters.

3. The multiplexing structure of claim 1 , wherein providing the resetting voltage includes providing Vprog at the first positive supply and providing Vprog-VDD at the first negative supply.

4. The multiplexing structure of claim 1 , wherein a nominal value of VDD is between 0.7-1V and a nominal value of Vprog is 2.5-3.5V.

5. The multiplexing structure of claim 2 , wherein the plurality of multiplexer input inverters are disabled during a programming operation of the plurality of resistive random access memories.

6. The multiplexing structure of claim 1 , wherein the plurality of first driving elements and the second driving element are controlled by a scan chain organization including one or more flip-flops.

7. The multiplexing structure of claim 1 , wherein the plurality of first driving elements and the second driving element are controlled by a memory bank organization including one or more bit lines and one or more word lines coupled to the plurality of first driving elements and the second driving element.

8. The multiplexing structure of claim 1 , further comprising:
an output inverter provided between the plurality of bottom electrodes and the multiplexer output, wherein the switchable voltage supply provides the power supply to the output inverter.

9. A field programmable gate array comprising:
a resistive random access memory including a top electrode and a bottom electrode;
a first transistor and a second transistor coupled to the top electrode;
a third transistor and a fourth transistor coupled to the bottom electrode, wherein the resistive random access memory is set when the first transistor and the fourth transistor are enabled, and wherein the resistive random access memory is reset when the second transistor and the third transistor are enabled;
a scan chain organization including:
a first flip-flop coupled to and controlling the first transistor and the fourth transistor; and
a second flip-flop coupled to and controlling the second transistor and the third transistor.

10. The field programmable gate array of claim 9 , further comprising one or more voltage supplies, wherein sources of the first transistor, second transistor, third transistor, and the fourth transistor are directly connected to the one or more voltage supplies without driving inverters.

11. The field programmable gate array of claim 9 , further comprising:
a constant voltage domain providing a power supply to the first transistor and the third transistor; and
a switchable voltage supply providing a power supply to the second transistor and the fourth transistor.

12. The field programmable gate array of claim 11 , wherein the resistive random access memory is part of a plurality of resistive random access memories and wherein the field programmable gate array further comprises:
a plurality of multiplexer inputs coupled to a plurality of top electrodes of the plurality of resistive random access memories; and
a multiplexer output coupled to a plurality of bottom electrodes of the plurality of resistive random access memories.

13. The field programmable gate array of claim 12 , wherein to set the resistive random access memory, the switchable voltage supply provides a setting voltage to the second transistor and the fourth transistor,
wherein to reset the resistive random access memory, the switchable voltage supply provides a resetting voltage, different from the setting voltage, to the second transistor and the fourth transistor, and
wherein one of the second transistor and the fourth transistor is coupled to a positive supply of the switchable voltage supply and the other of the second transistor and the fourth transistor is coupled to a negative supply of the switchable voltage supply.

14. The field programmable gate array of claim 13 , wherein providing the setting voltage includes providing −Vprog+2VDD at the positive supply and providing −Vprog+VDD at the negative supply, and
wherein providing the resetting voltage includes providing Vprog at the positive supply and providing Vprog−VDD at the negative supply.

15. A field programmable gate array comprising:
a resistive random access memory including a top electrode and a bottom electrode;
a first transistor and a second transistor coupled to the top electrode;
a third transistor and a fourth transistor coupled to the bottom electrode, wherein the resistive random access memory is set when the first transistor and the fourth transistor are enabled, and wherein the resistive random access memory is reset when the second transistor and the third transistor are enabled;
a memory bank organization including:
bit lines coupled to and controlling the first transistor and the third transistor; and
word lines coupled to and controlling the second transistor and the fourth transistor.

16. The field programmable gate array of claim 15 , further comprising one or more voltage supplies, wherein sources of the first transistor, second transistor, third transistor, and the fourth trans

Assignees

• Univ Utah Res Found
• Ecole Polytechnique Fed Lausanne Epfl
• Ecole Polytechnique Fed Lausanne Epfl

Inventors

• Gaillardon Pierre-Emanuel
• Tang Xifan
• Kim Gain
• De Micheli Giovanni
• Giacomin Edouard

Classifications

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• H03K19/1776

  for memories · CPC title

• G11C13/003

  Cell access · CPC title

• G11C13/0026

  Bit-line or column circuits · CPC title

• H03K19/1737 Primary

  using multiplexers (H03K19/1738 takes precedence) · CPC title