High-performance low-power near-Vt resistive memory-based FPGA

Patent metadata

Field	Value
Publication number	US-9276573-B2
Application number	US-201414444422-A
Country	US
Kind code	B2
Filing date	Jul 28, 2014
Priority date	Jul 28, 2014
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

A Field Programmable Gate Array (FPGA) of the island-type comprising a plurality of cluster-based Configurable Logic Blocks (CLBs), whereby each of the cluster-based CLBs is surrounded by a global routing structure formed by a plurality of multiplexers and pass/transmission-gates organized in Switch Boxes (SBs) and Connection Blocks (CBs), the switch boxes and the connection blocks comprising at least a first plurality of resistive memories inserted in a data path of a first routing architecture of the switch boxes and the connection blocks. Each CLB contains Basic Logic Elements (BLEs), as well as local routing resources.

First claim

What is claimed is:

1. A Field Programmable Gate Array (FPGA) of the island-type comprising a plurality of cluster-based Configurable Logic Blocks (CLBs),
wherein each of the cluster-based CLBs is surrounded by a global routing structure formed by a plurality of multiplexers and pass/transmission-gates organized in Switch Boxes (SBs) and Connection Blocks (CBs), the switch boxes and the connection blocks comprising at least a first plurality of resistive memories inserted in a data path of a first routing architecture of the switch boxes and the connection blocks,
wherein each CLB contains Basic Logic Elements (BLEs), as well as local routing resources,
each one of the local routing resources comprising at least a local routing multiplexer or a crossbar which route signals from the CLB inputs and the BLE outputs to the BLE inputs, each local routing multiplexer or crossbar comprising at least a plurality of Resistive Memories (RMs) inserted in a data path of a routing architecture of the local routing multiplexer, thereby being connected to inputs and outputs of the local routing multiplexer, and

each switch box and connection block comprises at least a group of the plurality of multiplexers, arranged to realize at least an interconnection.

2. The field programmable gate array of claim 1 , wherein each BLE comprises
at least a Look-Up Table (LUT),
a D Flip-Flop (DFF), and
a corresponding multiplexer, which selects either a combinational version or a sequential version of the LUT output, each LUT being based on at least a plurality of non-volatile scan-chain SRAMs connected in series, and the corresponding multiplexer comprising at least a second plurality of Resistive Memories (RMs) inserted in a data path of a second routing architecture of the corresponding multiplexer.

3. The field programmable gate array of claim 2 , wherein the LUT comprises a decoding multiplexer exploiting standard CMOS techniques and transistors and a plurality of storage elements exploiting at least a plurality of resistive memories,
the decoding multiplexer being configured to route information of one of the plurality of storage elements to the LUT output,
each one of the plurality of the storage elements comprises a flip-flop structure or a scan chain SRAM exploiting standard CMOS techniques and transistors combined with a plurality of resistive memories.

4. The field programmable gate array of claim 2 , wherein for each multiplexer
from the plurality of multiplexers forming the global routing structure,
from the corresponding multiplexer related to each BLE, and
from the local routing multiplexer of the local routing resources,
the plurality of resistive memories are organized in a tree based hierarchy, and
the field programmable gate array further comprises a plurality of programming transistors providing an access to the resistive memories during the programming phase.

5. The field programmable gate array of claim 3 , wherein for each multiplexer
from the plurality of multiplexers forming the global routing structure,
from the corresponding multiplexer related to each BLE, and
from the local routing multiplexer of the local routing resources,
the plurality of resistive memories are organized in a tree based hierarchy, and
the field programmable gate array further comprises a plurality of programming transistors providing an access to the resistive memories during the programming phase.

6. A method for configuring a Resistive Memory (RM) in a field programmable gate array of the island-type that comprises Basic Logic Elements, each of which comprises at least a Look-Up Table based on at least a plurality of non-volatile scan-chain SRAMs connected in series, each Basic Logic Element further comprising a corresponding multiplexer, wherein the corresponding multiplexer comprises at least a plurality of Resistive Memories inserted in a data path of a routing architecture of the corresponding multiplexer, the plurality of Resistive Memories including the Resistive Memory to configure, the method, comprising:
serially loading a program bitstream to the programming scan-chain SRAMs, sequentially configuring each stage of the corresponding multiplexer,
when a determined program bit is loaded in the programming scan-chain SRAMs for a determined stage, turning on a corresponding programming transistor of the Resistive Memory, and turning off the corresponding programming transistor after programming,
wherein a programming voltage V prog for the Resistive Memory is larger than a supply voltage Vdd according to the following equation:
V prog =λ·Vdd

wherein a value of λ must be set according to λ>1.

7. The method of claim 6 , further comprising setting λ to 1.2, thereby providing a slack of 20% between Vdd and V prog .

8. The method of claim 6 , further comprising
a sizing of the programming transistor to obtain an optimal size of the programming transistor, the sizing involving
determining the size of buffers (Winv) that drive the multiplexer, a capacitive load (CL) of this multiplexer and the programming voltage (Vprog);
determining the number of stages of the multiplexer;
extracting process parameters (Ids, Rmin, Coff) of a transistor intended for use in a circuit design of the Resistive Memories; and
applying

W

prog
,
opt

=

n
⁢

⁢

V
prog

⁢

C
L

⁢

W
inv

(

2
⁢
n

+
1

)

⁢

I
d

⁢

R
min

⁢

C
off

to identify an optimal value of a width of the programming transistor (Wprog,opt), wherein
R min denotes the equivalent resistance of a minimum size inverter, C off is the parasitic capacitance of a minimum width programming transistor in off state, I d is the driving current of a minimum width transistor, n is the number of stages of resistive memories on which the multiplexer is based.

Assignees

• Ecole Polytech
• Ecole Polytech

Inventors

• Gaillardon Pierre-Emmanuel
• Tang Xifan
• De Micheli Giovanni

Classifications

• H03K19/1776

  for memories · CPC title

• H03K19/0013 Primary

  in field effect transistor circuits · CPC title

• H03K19/0941

  of complementary type · CPC title

• H03K19/1774

  for global signals, e.g. clock, reset · CPC title

• H03K19/17728

  Reconfigurable logic blocks, e.g. lookup tables · CPC title