Frequency-divider circuitry

Patent metadata

Field	Value
Publication number	US-10348275-B2
Application number	US-201816039760-A
Country	US
Kind code	B2
Filing date	Jul 19, 2018
Priority date	Jul 26, 2017
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

There is disclosed configurable frequency-divider circuitry for generating a target signal of a frequency Fr/Di based on a reference signal of a frequency Fr, where Di is an integer divider ratio, the frequency-divider circuitry comprising: N divider stages organised into a ring, each stage configured to receive an input signal and generate an output signal, with the output signal of each successive stage in the ring being the input signal of the next stage in the ring, wherein: the ring of stages is controlled by the reference signal so that the output signals are governed by the reference signal; the target signal is one of the output signals or a signal derived therefrom; and at least one of the stages is a configurable stage, whose mode of operation is configurable based on a configuration signal to configure the value of Di.

First claim

The invention claimed is:

1. Configurable frequency-divider circuitry for generating a target signal TS of a frequency Fr/Di based on a reference signal RS of a frequency Fr, where Di is an integer divider ratio, the frequency-divider circuitry comprising:
N divider stages organized into a ring, each divider stage having an input node and an output node and configured to receive an input signal IS at its input node and generate an output signal OS at its output node, with the divider stages connected together so that the output signal OS of each successive divider stage in the ring forms the input signal IS of the next divider stage in the ring,
wherein:
each divider stage comprises a logic high voltage reference and a logic low voltage reference;
each said divider stage is arranged to operate in at least one of a mode A, a mode B, a mode C and a mode I;
each divider stage comprises a pull-up path which extends between its output node and its logic high voltage reference, with a transistor connected therealong and controlled by the input signal IS of that divider stage if that divider stage is arranged to operate in said mode I or said mode C, or with a transistor connected therealong and controlled by the input signal IS of that divider stage and another transistor connected therealong and controlled by the reference signal RS if that divider stage is arranged to operate in said mode A or said mode B;
each divider stage comprises a pull-down path which extends between its output node and its logic low voltage reference, with a transistor connected therealong and controlled by the input signal IS of that divider stage if that divider stage is arranged to operate in said mode I or said mode A, or with a transistor connected therealong and controlled by the input signal IS of that divider stage and another transistor connected therealong and controlled by the reference signal RS if that divider stage is arranged to operate in said mode B or said mode C;
at least one of the divider stages is a configurable divider stage and comprises said pull-up path with the transistor connected therealong and controlled by the input signal IS of that divider stage and the transistor connected therealong and controlled by the reference signal RS, a further pull-up path which extends between its output node and its logic high voltage reference with a transistor connected therealong and controlled by the input signal IS of that divider stage and another transistor connected therealong and controlled by a first mode-configuration signal M 1 , said pull-down path with the transistor connected therealong and controlled by the input signal IS of that divider stage and the transistor connected therealong and controlled by the reference signal RS, and a further pull-down path which extends between its output node and its logic low voltage reference with a transistor connected therealong and controlled by the input signal IS of that divider stage and another transistor connected therealong and controlled by a second mode-configuration signal M 2 ;
for each said divider stage having a said transistor connected along a said pull-up path and controlled by the reference signal and a said transistor connected along a said pull-down path and also controlled by the reference signal, those transistors are configured to be controlled by the reference signal so that when one of those transistors is OFF the other of those transistors is ON;
the target signal TS is one of the output signals OS or a signal derived therefrom; and
the configurable frequency-divider circuitry further comprises a configuration unit operable, for each configurable divider stage, to configure the voltage levels of its first and second mode-configuration signals M 1 and M 2 to control which of said modes that configurable divider stage operates in and therefore a combination of said modes in which the N divider stages operate, and thereby configure a value of Di.

2. The configurable frequency-divider circuitry according to claim 1 , wherein each of a plurality or all or all but one of the divider stages is a said configurable stage.

3. The configurable frequency-divider circuitry according to claim 1 , wherein the configuration unit is operable, for each configurable divider stage, to provide its first and second mode-configuration signals M 1 and M 2 so as to turn its transistors controlled by the first and second-mode configuration signals M 1 and M 2 :
for said mode A, OFF and ON respectively;
for said mode B, OFF and OFF respectively;
for said mode C, ON and OFF respectively; and
for said mode I, ON and ON respectively.

4. The configurable frequency-divider circuitry according to claim 1 , comprising a selector operable to:
receive the output signals OS from some or all of the divider stages, and to output one or more of the output signals as the target signal TS in dependence upon a selection signal; or
receive the output signals OS from some or all of the divider stages via a buffer, and to output one or more of the output signals received via the buffer as the target signal TS in dependence upon a selection signal,
and further comprising a control unit operable to provide the selection signal.

5. The configurable frequency-divider circuitry according to claim 4 , wherein the a control unit is operable to cause the configuration unit to vary the value of Di and/or to cause the selector to vary the selection signal to change which one or more of the output signals or buffered output signals is output as the target signal TS.

6. The configurable frequency-divider circuitry according to claim 1 , further comprising a control unit operable to cause the configuration unit to vary the value of Di over time so that the value of Di alternates over time between two values Di 1 and Di 2 and when averaged over time has a value which is a time average of Dil and Di 2 and has a fractional component.

7. The configurable frequency-divider circuitry according to claim 1 , wherein the reference signal RS and the target signal TS are clock signals.

8. The configurable frequency-divider circuitry according to claim 1 , wherein, for at least one or each said configurable divider stage, its said pull-up paths are separate parallel pull-up paths and its said pull-down paths are separate parallel pull-down paths.

9. The configurable frequency-divider circuitry according to claim 2 , wherein:
each configurable divider stage is formed by a circuitry structure; and
the circuitry structures of the configurable divider stages are the same as one another.

10. The configurable frequency-divider circuitry according to claim 1 , wherein:
for each divider stage, the logic high voltage reference provides a digital 1 voltage level and the logic low voltage reference provides a digital 0 voltage level;
the reference signal RS, the input signals IS and the output signals OS are digital signals;
for each divider stage arranged to operate in said mode A, a said pull-up path of that divider stage is configured to be conductive if a Boolean expression /IS./RS evaluates to a digital 1 value and a said pull-down path of that divider stage is configured to be conductive if a Boolean expression IS evaluates to a digital 1 value;
for each divider stage arranged to operate in mode B, a said pull-up path of that divider stage is configured to be conductive if a Boolean expression /IS./RS evaluates to a digital 1 value and a said pull-down path of that divider stage is configured to be conductive if a Boolean expression IS.RS evaluates to a digital 1 value;
for each divider stage arranged to operate in mode C, a said pull-up path of that divider stage is configured to be conductive if a Boolean e

Assignees

• Cirrus Logic Int Semiconductor Ltd
• Cirrus Logic Inc

Inventors

• San Martin Molina Dario
• Bates Gordon James

Classifications

• H03L7/193

  the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider · CPC title

• H03K5/00006 Primary

  Changing the frequency (modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68) · CPC title

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• H03K21/00

  Details of pulse counters or frequency dividers · CPC title

• H03K23/00

  Pulse counters comprising counting chains; Frequency dividers comprising counting chains (H03K29/00 takes precedence) · CPC title