Split gate non-volatile memory (NVM) with improved programming efficiency

Patent metadata

Field	Value
Publication number	US-10347773-B2
Application number	US-201715807539-A
Country	US
Kind code	B2
Filing date	Nov 8, 2017
Priority date	Nov 8, 2017
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

Device and method of forming a non-volatile memory (NVM) device are disclosed. The NVM device includes NVM cells disposed on a substrate in a device region. The NVM cell includes a floating gate (FG) with first and second FG sidewalls disposed on the substrate and an intergate dielectric layer disposed over the FG and substrate. Re-entrants are disposed at corners of the intergate dielectric which are filled by dielectric re-entrant spacers. An access gate (AG) with first and second AG sidewalls is disposed on the substrate adjacent to the FG such that the second AG sidewall is adjacent to a first FG sidewall and separated by the intergate dielectric layer and the re-entrant spacers prevent AG from filling the re-entrants. A first source/drain (S/D) region is disposed in the substrate adjacent to the first AG sidewall and a second S/D region is disposed in the substrate adjacent to the second FG sidewall.

First claim

The invention claimed is:

1. A method of forming a non-volatile memory (NVM) cell, comprising:
providing a substrate prepared with a device region;
forming a floating gate (FG) on the substrate, wherein the FG includes first and second FG sidewalls;
forming an intergate dielectric layer on the substrate, wherein the intergate dielectric layer covers the FG and substrate, and the intergate dielectric layer comprises re-entrants at corners of the intergate dielectric layer respectively located at a first interface between the first FG sidewall and the substrate and at a second interface between the second FG sidewall and the substrate;
forming dielectric re-entrant spacers in the re-entrants, wherein the dielectric re-entrant spacers respectively fill the re-entrants at the corners of the intergate dielectric layer;
forming an access gate (AG) on the substrate adjacent to the FG, wherein the AG includes first and second AG sidewalls, wherein the second AG sidewall is adjacent to the first FG sidewall and separated by the intergate dielectric layer, and wherein the re-entrant spacers prevent the AG from filling the re-entrants;
forming a second source/drain (S/D) region in the substrate adjacent to the second FG sidewall; and
forming a first S/D region in the substrate adjacent to the first AG sidewall,
wherein forming the FG comprises:
forming a FG dielectric layer on the substrate;
forming a FG electrode layer over the FG dielectric layer; and
forming a FG polysilicon oxide on top of the FG and an oxidation layer on the first and second FG sidewalls and substrate surfaces by oxidizing the FG and substrate surfaces.

2. The method of claim 1 , wherein providing the substrate comprises:
doping the substrate with first polarity type dopants;
forming an isolation well with first polarity type dopants in the substrate; and
forming a device well with second polarity type dopants.

3. The method of claim 2 , wherein the first polarity type dopants are p-type dopants and the second polarity type dopants are n-type dopants.

4. The method of claim 1 , wherein forming the AG comprises forming an AG electrode in between the FG and the first S/D region, the AG electrode overlaps a portion of the FG and a portion of the first S/D region, and is separated by the FG polysilicon oxide, the oxidation layer and the intergate dielectric layer, and wherein the oxidation layer and the intergate dielectric layer under the AG serve as an AG dielectric.

5. The method of claim 1 , wherein the first S/D region serves as a drain terminal, and the second S/D region serves as a source terminal and is coupled to a common source line (SL).

6. A method of forming a non-volatile memory (NVM) device, comprising:
providing a substrate prepared with a memory region;
forming at least a memory cell pair in the memory region, wherein the memory cell pair includes first and second memory cells, and wherein forming each of the first and second memory cells includes
forming a first gate on the substrate, wherein the first gate includes first and second sidewalls,
forming an intergate dielectric layer over the first gate and the substrate, wherein the intergate dielectric layer includes re-entrants at corners of the intergate dielectric layer,
forming dielectric re-entrant spacers in the re-entrants, wherein the dielectric re-entrant spacers respectively fill the re-entrants at the corners of the intergate dielectric layer respectively located at a first interface between the first sidewall of the first gate and the substrate and at a second interface between the second sidewall of the first gate and the substrate,
forming a second gate on the substrate adjacent to the first gate, wherein the second gate includes first and second sidewalls, wherein the second sidewall of the second gate is adjacent to the first sidewall of the first gate and separated by the intergate dielectric layer, and wherein the re-entrant spacers prevent the second gate from filling the re-entrants,
forming a first source/drain (S/D) region in the substrate adjacent to the first sidewall of the second gate, and
forming a second S/D region in the substrate adjacent to the second sidewall of the first gate,

wherein forming the first gate comprises:
forming a gate dielectric layer on the substrate;
forming a gate electrode layer over the gate dielectric layer; and
forming a gate polysilicon oxide on top of the first gate and an oxidation layer on the first and second sidewalls of the first gate and substrate surfaces by oxidizing the first gate and substrate surfaces.

7. The method of claim 6 , wherein providing the substrate comprises:
doping the substrate with first polarity type dopants;
forming an isolation well with first polarity type dopants in the substrate; and
forming a device well with second polarity type dopants.

8. The method of claim 7 , wherein the first polarity type dopants are p-type dopants and the second polarity type dopants are n-type.

9. The method of claim 8 , wherein the first gate serves as a floating gate (FG), and the second gate serves as an access gate (AG).

10. The method of claim 9 , wherein forming the AG comprises forming an AG electrode in between the FG and the first S/D region, the AG electrode overlaps a portion of the FG and a portion of the first S/D region, the AG electrode is separated by the FG polysilicon oxide, the oxidation layer and the intergate dielectric layer, and wherein the oxidation layer and the intergate dielectric layer under the AG serve as an AG dielectric.

11. The method of claim 6 , wherein the first S/D region serves as a drain terminal, the second S/D region serves as a source terminal, and the source terminal is a common source terminal of the memory cell pair and is coupled to a common source line (SL).

12. The method of in claim 6 , wherein the first and second gates serve as a common split gate conductor for a plurality of memory cells.

13. A non-volatile memory (NVM) cell comprising:
a substrate prepared with a device region;
a floating gate (FG) disposed on the substrate, wherein the FG includes first and second FG sidewalls;
an intergate dielectric layer disposed on the substrate, wherein the intergate dielectric layer covers the FG and substrate, and the intergate dielectric layer comprises re-entrants at corners of the intergate dielectric layer;
dielectric re-entrant spacers disposed in the re-entrants, wherein the dielectric re-entrant spacers respectively fill the re-entrants at the corners of the intergate dielectric layer respectively located at a first interface between the first FG sidewall and the substrate and at a second interface between the second FG sidewall and the substrate;
an access gate (AG) disposed on the substrate adjacent to the FG, wherein the AG includes first and second AG sidewalls, wherein the second AG sidewall is adjacent to the first FG sidewall and separated by the intergate dielectric layer, wherein the re-entrant spacers prevent AG from filling the re-entrants;
a second S/D region disposed in the substrate adjacent to the second FG sidewall; and
a first S/D region disposed in the substrate adjacent to the first AG sidewall;
wherein the FG further includes:
a FG dielectric layer disposed on the substrate;
a FG electrode layer disposed over the FG dielectric layer;
a FG polysilicon oxide disposed on top of the FG; and
an oxidation layer disposed on the first and second FG sidewalls and substrate surfaces.

14. The NVM cell of claim 13 , wherein the substrate is doped with first polarity type dopants, an isolation well with first polarity type dopants is fo

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Si Wei
• Wang Zeng
• Koo Jeoung Mo
• Purakh Raj Verma

Classifications

• H10D64/01306

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon · CPC title

• G11C16/34

  Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention · CPC title

• H01L27/11517

  Electricity · mapped topic

• H01L21/28035

  Electricity · mapped topic

• H01L29/7883 Primary

  Electricity · mapped topic