Semiconductor structure and a fabricating method thereof

Patent metadata

Field	Value
Publication number	US-9349815-B2
Application number	US-201414488295-A
Country	US
Kind code	B2
Filing date	Sep 17, 2014
Priority date	Sep 17, 2014
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

A gate structure is provided. The gate structure includes a substrate, a gate disposed on the substrate and a gate dielectric layer disposed between the substrate and the gate, wherein the gate dielectric layer is in the shape of a barbell. The barbell has a thin center connecting to two bulging ends. Part of the bulging ends extends into the gate and the substrate.

First claim

What is claimed is:

1. A fabricating method of a semiconductor structure comprising:
forming a gate and a dielectric layer on a substrate, wherein the dielectric layer is disposed between the gate and the substrate;
removing part of the dielectric layer to form at least two recesses, wherein each of the recesses is defined by part of the gate, part of the dielectric layer and part of the substrate;
performing a first oxide formation process to transform the gate, the dielectric layer and the substrate defining the recesses into a first silicon oxide layer; and
after the first oxide formation process, performing a second oxide formation process to form a second silicon oxide layer filling the recesses and covering the first silicon oxide layer.

2. The fabricating method of a semiconductor structure of claim 1 , wherein the two recesses are formed by a wet etch process.

3. The fabricating method of a semiconductor structure of claim 1 , wherein the first silicon oxide layer fills the recesses.

4. The fabricating method of a semiconductor structure of claim 1 , wherein the first silicon oxide layer extends into the gate, the substrate, and the dielectric layer.

5. The fabricating method of a semiconductor structure of claim 1 , wherein the first oxide formation process comprises a rapid thermal oxidation process.

6. The fabricating method of a semiconductor structure of claim 1 , wherein the second silicon oxide layer is formed by a high temperature oxidation process or an in-situ steam generation process.

7. The fabricating method of a semiconductor structure of claim 1 , wherein the two recesses extend into the dielectric layer, and are covered by the gate.

8. The fabricating method of a semiconductor structure of claim 1 , further comprising:
forming two source/drain regions in the substrate at a side of the gate.

Assignees

• United Microelectronics Corp

Inventors

• Tseng Kuan-Yi
• Chen Tzu-Ping
• Chang Chun-Lung
• Lee Chih-Haw
• Huang Wei-Shiang
• Chen Chien-Hung

Classifications

• H10D64/01332

  Making the insulator · CPC title

• H10D64/01306

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon · CPC title

• H10D30/601

  having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  (lightly doped source or drain extensions for TFTs H10D30/6715) · CPC title

• H10D30/0227

  having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET · CPC title

• H10D30/0223

  having source and drain regions or source and drain extensions self-aligned to sides of the gate · CPC title