Method for manufacturing a transistor

Patent metadata

Field	Value
Publication number	US-2016268402-A1
Application number	US-201615066396-A
Country	US
Kind code	A1
Filing date	Mar 10, 2016
Priority date	Mar 11, 2015
Publication date	Sep 15, 2016
Grant date	—

Abstract

A method comprises arranging a stack, on a semiconductor substrate, comprising a sacrificial layer and an insulating layer. The insulator layer is at least partially arranged between the semiconductor substrate and the sacrificial layer. A recess is formed within the stack. The recess extends through the stack to the semiconductor substrate so that the recess at least partially overlaps with a surface of the collector region of the semiconductor substrate. The collector region extends from a main surface of the semiconductor substrate into the substrate material. The method further comprises generating a base structure at the collector region and in the recess. The base structure contacts and covers the collector region within the recess of the sacrificial layer. The method further comprises generating an emitter structure at the base structure. The emitter structure contacts and at least partially covers the base structure within the recess of the sacrificial layer.

First claim

1 . Method for manufacturing a transistor, the method comprising:
arranging a stack on a semiconductor substrate, the stack comprising a sacrificial layer and an insulator layer; the insulator layer at least partially being arranged between the semiconductor substrate and the sacrificial layer, wherein a recess is formed within the stack, wherein the recess extends through the stack to the semiconductor substrate, so that the recess at least partially overlaps with a collector region of the semiconductor substrate, and wherein the collector region extends from a main surface of the semiconductor substrate into a substrate material of the semiconductor substrate; generating a base structure at the collector region and in the recess, wherein the base structure contacts and covers the collector region within the recess of the sacrificial layer; generating an emitter structure at the base structure, wherein the emitter structure contacts and at least partially covers the base structure within the recess of the sacrificial layer; removing the sacrificial layer at least partially such that a lateral surface region of the base structure is exposed; and generating a doped electrode layer by epitaxially growing a semiconductor material to the exposed lateral surface region of the base structure, such that the doped electrode layer connects the lateral surface region of the base structure.

2 . The method according to claim 1 , wherein, during generating the doped electrode layer, the doped electrode layer is grown monocrystalline at the base structure in a lateral direction perpendicular to a surface normal of the semiconductor substrate.

3 . The method according to claim 1 , wherein, during generating the base structure, the base structure is deposited extensively in the recess such that the base structure is aligned with respect to the collector region and with respect to the recess.

4 . The method according to claim 1 , further comprising:
generating a spacer structure at the base structure and in the recess at a main surface region of the base structure and before the emitter structure is generated; wherein the emitter structure is generated in the recess at a portion of the main surface region of the base structure uncovered by the spacer structure.

5 . The method according to claim 4 , further comprising:
arranging an insulator material at the emitter structure such that the emitter structure is encapsulated by the insulator material, the spacer structure and the base structure.

6 . The method according to claim 1 , wherein the stack further comprises an electrode seed layer arranged between the insulator layer and the sacrificial layer, wherein the insulator layer is arranged between the semiconductor substrate and the electrode seed layer, and wherein the sacrificial layer spaces the electrode seed layer from the recess;
wherein, during removing the sacrificial layer, a surface region of the electrode seed layer is exposed; and wherein, during generating the doped electrode layer, the semiconductor material is grown to the exposed surface region of the electrode seed layer, such that the doped electrode layer connects the exposed lateral surface region of the base structure and the surface region of the electrode seed layer.

7 . The method according to claim 6 , wherein, during generating the doped electrode layer, the doped electrode layer is grown amorphous or polycrystalline at the electrode seed layer along a thickness direction parallel to a direction of a normal of the main surface.

8 . The method according to claim 1 , wherein arranging the stack comprises:
providing the semiconductor substrate; arranging an insulator layer at the semiconductor substrate; arranging the electrode seed layer at the insulator layer; arranging the sacrificial layer at the electrode seed layer; removing the sacrificial layer and the electrode seed layer in a separating region exceeding a region of the recess; and re-arranging the sacrificial layer in the separating region such that the recess is formed and such that the electrode seed layer is separated from the recess by the re-arranged sacrificial layer.

9 . The method according to claim 8 , wherein during arranging the electrode seed layer, the electrode seed layer is arranged by depositing an amorphous silicon material or a polysilicon material at the insulator layer.

10 . The method according to claim 8 , wherein, during removing the electrode seed layer, the electrode seed layer is removed such that a distance between the recess and the electrode seed layer of at least 5 nm and at most 100 nm is obtained.

11 . The method according to claim 1 , wherein arranging the stack comprises:
generating the collector region in the recess and in the semiconductor substrate by implantation, wherein the implantation is performed through the insulator layer.

12 . The method according to claim 1 , wherein arranging the stack further comprises arranging the sacrificial layer by depositing a silicon nitride material at the insulator layer or at an electrode seed layer.

13 . The method according to claim 1 , wherein arranging the stack further comprises arranging the insulator layer such that a thickness of the insulator layer of at least 15 nm and at most 200 nm along a thickness direction parallel to a direction of a normal of the main surface of the semiconductor substrate is obtained.

14 . The method according to claim 1 , wherein, during generating the base structure, the base structure is grown such that a thickness of the base structure of at least 40 nm and at most 50 nm along a thickness direction parallel to a direction of a normal of the main surface of the semiconductor substrate is obtained.

15 . The method according to claim 1 , wherein, during generating the doped electrode layer, the doped electrode layer is generated by epitaxially growing using a silicon material and a boron material.

16 . The method according to claim 1 , wherein generating the doped electrode layer is performed without a temperature annealing.

17 . A transistor comprising:
a semiconductor substrate comprising a collector region extending from a main surface of the semiconductor substrate into a substrate material of the semiconductor substrate; a base structure arranged at the collector region along a thickness direction parallel to a direction of a normal of the main surface of the semiconductor substrate; an emitter structure arranged at the base structure averted from the semiconductor substrate and along the thickness direction; and a doped electrode layer arranged at a lateral surface region of the base structure and along a lateral direction perpendicular to the thickness direction; wherein the doped electrode layer and the base structure form a monocrystalline connection.

18 . The transistor according to claim 17 , wherein the doped electrode layer is doped in a region thereof adjacent to the base structure.

19 . The transistor according to claim 17 , wherein the doped electrode layer comprises a boron doped silicon material.

20 . The transistor according to claim 17 , wherein the doped electrode layer is monocrystalline at a region adjacent to the base structure and amorphous or polycrystalline at a region spaced from the base structure.

21 . The transistor according to claim 17 , wherein the base structure comprises a silicon material and at least one of a germanium material, a boron material, or a carbon material.

Assignees

• Infineon Technologies Dresden Gmbh

Inventors

• Dahl Claus
• Tschumakow Dmitri Alex

Classifications

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10D62/822

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title

• H10D64/281

  Base electrodes for bipolar transistors · CPC title

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title