Semiconductor device that facilitates a reduction in the occurrences of cracking in a semiconductor layer accompanying thermal stress

Patent metadata

Field	Value
Publication number	US-10347725-B2
Application number	US-201514956977-A
Country	US
Kind code	B2
Filing date	Dec 2, 2015
Priority date	Jun 23, 2015
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

An emitter electrode includes a first electrode layer, a second electrode layer, and a third electrode layer. The first to third electrode layers are laid in this order on an emitter layer. A solder layer is further laid on the third electrode layer. The first electrode layer covers the emitter layer and a gate oxide film in a front surface of a semiconductor chip. A first electroconductive material forming the first electrode layer has AlSi as its main component. A second electroconductive material forming the second electrode layer has a linear expansion coefficient different from that of the first electroconductive material and is lower in mechanical strength than the first electroconductive material. A third electroconductive material constituting the third electrode layer has a linear expansion coefficient different from that of the first electroconductive material and has solder wettability higher than that of the first electrode layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a collector, cathode, or drain electrode formed on a back surface of a semiconductor chip;
a semiconductor layer including an n-type drift layer and at least one n-type source layer formed on a front surface of the semiconductor chip; and
a first electrode, formed on the front surface of the semiconductor chip, the first electrode including:
a first electrode layer provided on the front surface of the semiconductor chip and formed of a first electroconductive material including AlSi in which the proportion of Si is higher than 1%;
a second electrode layer laid on the first electrode layer and formed of a second electroconductive material including Al, a proportion of Si in the second electrode layer being less than the proportion of Si in the first electroconductive layer, and the second electrode layer having a linear expansion coefficient different from that of the first electroconductive material and being lower in mechanical strength than the first electroconductive material; and
a third electrode layer laid directly on the second electrode layer and formed of a third electroconductive material having a linear expansion coefficient different from that of the first electroconductive material and having solder wettability higher than that of the first electroconductive material, wherein

a guard ring is provided in the front surface of the semiconductor layer, the guard ring surrounding the first electrode layer as seen in a plan view, and
the second electrode layer is provided by being extended outward relative to the third electrode layer so that a peripheral edge of the second electrode layer surrounds a peripheral edge of the third electrode layer as seen in the plan view.

2. The semiconductor device according to claim 1 , further comprising a barrier metal layer provided between the first electrode layer and the second electrode layer and formed of an electroconductive material higher in mechanical strength than the second electroconductive material.

3. The semiconductor device according to claim 2 , wherein the electroconductive material of the barrier metal layer is Ti or a Ti alloy.

4. The semiconductor device according to claim 1 , wherein the first electroconductive material is AlSi and the second electroconductive material is pure aluminum.

5. The semiconductor device according to claim 4 , wherein the first electroconductive material is AlSi in which the proportion of Si is higher than 1%.

6. The semiconductor device according to claim 1 , wherein the first electroconductive material is AlSiCu in which the proportion of Si is higher than 1%, and which contains Cu.

7. The semiconductor device according to claim 1 , further comprising:
a solder layer laid on the third electrode layer; and
a lead frame soldered to the third electrode layer by means of the solder layer.

8. The semiconductor device according to claim 1 , wherein the material of the semiconductor layer is a wide-bandgap semiconductor.

9. The semiconductor device according to claim 1 , further comprising a channel stopper provided outside the guard ring.

10. A semiconductor device comprising:
a collector, cathode, or drain electrode formed on a back surface of a semiconductor chip;
a semiconductor layer including an n-type drift layer and at least one n-type source layer formed on a front surface of the semiconductor chip; and
a first electrode, formed on the front surface of the semiconductor chip, the first electrode including:
a first electrode layer provided on the front surface of the semiconductor chip and formed of either AlCu in which the proportion of Cu is higher than 1% or AlSiCu in which the proportion of Si is higher than 1%; and
a second electrode layer laid on the first electrode layer and formed of Cu, wherein

a guard ring is provided in the front surface of the semiconductor layer, the guard ring surrounding the first electrode layer as seen in a plan view, and
the first electrode layer is provided by being extended outward relative to a peripheral edge of the second electrode layer as seen in the plan view.

11. The semiconductor device according to claim 10 , wherein the material of the first electrode layer is AlCu in which the proportion of Cu is higher than 1%.

12. The semiconductor device according to claim 10 , wherein the material of the first electrode layer is AlSiCu in which the proportion of Si is higher than 1%.

13. The semiconductor device according to claim 10 , further comprising a barrier metal layer provided between the first electrode layer and the second electrode layer and formed of a material higher in mechanical strength than the second electroconductive material.

14. The semiconductor device according to claim 13 , wherein the material of the barrier metal layer is Ti or a Ti alloy.

15. The semiconductor device according to claim 10 , further comprising:
a solder layer laid on the second electrode layer; and
a lead frame soldered to the second electrode layer by means of the solder layer.

16. The semiconductor device according to claim 10 , wherein the material of the semiconductor layer is a wide-bandgap semiconductor.

17. The semiconductor device according to claim 10 , further comprising a channel stopper provided outside the guard ring.

Assignees

• Mitsubishi Electric Corp

Inventors

• Nobukuni Akihiko
• Oki Hirofumi
• Tomomatsu Yoshifumi

Classifications

• H10W90/763

  between laterally-adjacent chips · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/07351

  characterised by changes in properties of the die-attach connectors during connecting · CPC title

• H10W72/5475

  multiple bond wires connected to common bond pads at both ends of the wires · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title