System and method for routing signals in complex quantum systems

Patent metadata

Field	Value
Publication number	US-10347605-B2
Application number	US-201715823817-A
Country	US
Kind code	B2
Filing date	Nov 28, 2017
Priority date	Nov 28, 2017
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

Embodiments of the present invention disclose a computer system having a plurality of quantum circuits arranged in a two-dimensional plane-like structure, the quantum circuits comprising qubits and busses (i.e., qubit-qubit interconnects), and a method of formation therefor. A quantum computer system comprises a plurality of quantum circuits arranged in a two-dimensional pattern. At least one interior quantum circuit, not along the perimeter of the two-dimensional plane of the plurality of quantum circuits, contains a bottom chip, a device layer, a top chip, and a routing layer. A signal wire connects the device layer to the routing layer, wherein the signal wire breaks the two dimensional plane, for example, the signal wire extends into a different plane.

First claim

What is claimed is:

1. A quantum computer system comprising:
a plurality of quantum circuits arranged in a two-dimensional layout; and
wherein the plurality of quantum circuits includes at least one interior quantum circuit that is not along a perimeter of the two-dimensional layout, wherein the at least one interior quantum circuit comprises a plurality of layers, a top layer of the plurality of layers including a through hole to a bottom layer of the plurality of layers; and
a signal wire positioned at least partially within the through hole and connecting the bottom layer to the top layer.

2. The quantum computer system of claim 1 , wherein the bottom layer of the plurality of layers comprises a bottom chip having a device layer and the top layer of the plurality of layers comprises a top chip having a routing layer; and
wherein the signal wire communicatively connects the device layer of the bottom chip to the routing layer of the top chip, and wherein the signal wire is not parallel to a plane of the two dimensional layout.

3. The quantum computer system of claim 2 , wherein the through hole is formed by reactive ion etching or by laser milling.

4. The quantum computer system of claim 3 , wherein the through hole has a diameter less than or equal to 1000 μm.

5. The quantum computer system of claim 2 , wherein the interior quantum circuit further comprises:
a first bonding pad located on the device layer; and
a second bonding pad located on the routing layer.

6. The quantum computer system of claim 5 , wherein the signal wire is connected to the first bonding pad and the second bonding pad.

7. A quantum computer system comprising:
a plurality of quantum circuits arranged in a two-dimensional layout, the plurality of quantum circuits including at least one interior quantum circuit that is not along a perimeter of the two-dimensional layout, wherein the at least one interior quantum circuit includes a device layer and a routing layer;
a signal wire that connects the device layer to the routing layer, wherein the signal wire extends out of the two-dimensional layout of the plurality of quantum circuits; and
a through hole formed in the routing layer, wherein the signal wire pass though the through hole.

8. The quantum computer system of claim 7 , wherein the through hole is formed by reactive ion etching or by laser milling.

9. The quantum computer system of claim 7 , wherein the through hole has a diameter less than or equal to 1000 μm.

10. The quantum computer system of claim 7 , wherein the interior quantum circuit further comprises:
a first bonding pad located on the device layer; and
a second bonding pad located on the routing layer.

11. The quantum computer system of claim 10 , wherein the signal wire is connected to the first bonding pad and the second bonding pad.

Assignees

• IBM

Inventors

• Sandberg Martin O
• Mckay David C
• Gumann Patryk M
• Paik Hanhee
• Gambetta Jay M

Classifications

• H10W90/752

  between stacked chips · CPC title

• H10W72/07536

  Soldering or alloying · CPC title

• H10W72/07523

  Active alignment, e.g. using optical alignment using marks or sensors · CPC title

• H10W72/07521

  Aligning · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title