Stacked chip package including substrate with recess adjoining side edge of substrate and method for forming the same

Patent metadata

Field	Value
Publication number	US-9633935-B2
Application number	US-201514697235-A
Country	US
Kind code	B2
Filing date	Apr 27, 2015
Priority date	Apr 28, 2014
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A stacked chip package is provided. The stacked chip package includes a first substrate having a first side and a second side opposite thereto. The first substrate includes a recess therein. The recess adjoins a side edge of the first substrate. A plurality of redistribution layers is disposed on the first substrate and extends onto the bottom of the recess. A second substrate is disposed on the first side of the first substrate. A plurality of bonding wires is correspondingly disposed on the redistribution layers in the recess, and extends onto the second substrate. A device substrate is disposed on the second side of the first substrate. A method of forming the stacked chip package is also provided.

First claim

What is claimed is:

1. A stacked chip package, comprising:
at least one first substrate having a first side and a second side opposite thereto, wherein the at least one first substrate comprises:
a recess in the at least one first substrate and adjoining a side edge of the at least one first substrate; and
a plurality of redistribution layers disposed on the at least one first substrate and extending onto a bottom of the recess, wherein at least two of the plurality of redistribution layers comprise an end extending into the recess, and the ends have an expanded portion;
at least one second substrate disposed on the first side of the at least one first substrate;
a plurality of bonding wires correspondingly disposed on the plurality of redistribution layers in the recess, and extending onto the at least one second substrate; and
at least one device substrate disposed on the second side of the at least one first substrate.

2. The stacked chip package as claimed in claim 1 , wherein the at least one device substrate comprises a plurality of first conducting pads therein, and the plurality of first conducting pads is electrically connected to the plurality of redistribution layers through a plurality of first conducting structures.

3. The stacked chip package as claimed in claim 1 , wherein the at least one device substrate is a chip.

4. The stacked chip package as claimed in claim 1 , wherein the at least one first substrate is a chip or an interposer.

5. The stacked chip package as claimed in claim 1 , wherein the at least one second substrate is a chip, an interposer or a circuit board.

6. The stacked chip package as claimed in claim 1 , further comprising a third substrate disposed on the first side of the at least one first substrate, wherein the at least one second substrate is located between the at least one first substrate and the third substrate.

7. The stacked chip package as claimed in claim 6 , wherein the third substrate comprises a plurality of second conducting pads, and the plurality of second conducting pads is electrically connected to the bonding wires through a plurality of second conducting structures.

8. The stacked chip package as claimed in claim 6 , wherein the third substrate is a chip, an interposer or a circuit board.

9. The stacked chip package as claimed in claim 1 , wherein at least two of the plurality of redistribution layers have different widths and/or lengths as viewed from a top view perspective.

10. A stacked chip package, comprising:
at least one first substrate having a first side and a second side opposite thereto, wherein the at least one first substrate comprises:
a recess in the at least one first substrate and adjoining a side edge of the at least one first substrate; and
a plurality of redistribution layers disposed on the at least one first substrate and extending onto a bottom of the recess;
at least one second substrate disposed on the first side of the at least one first substrate;
a plurality of bonding wires correspondingly disposed on the plurality of redistribution layers in the recess, and extending onto the at least one second substrate; and
at least one device substrate disposed on the second side of the at least one first substrate,
wherein at least two of the plurality of redistribution layers comprise an end extending into the recess, and the ends have an expanded portion, and wherein the expanded portions have different sizes and/or shapes.

11. A method for forming a stacked chip package, comprising:
providing at least one first substrate having a first side and a second side opposite thereto, wherein the at least one first substrate comprises:
a recess in the at least one first substrate and adjoining a side edge of the at least one first substrate; and
a plurality of redistribution layers disposed on the at least one first substrate and extending onto a bottom of the recess, wherein at least two of the plurality of redistribution layers comprise an end extending into the recess, and the ends have an expanded portion;
providing at least one second substrate on the first side of the at least one first substrate;
forming a plurality of bonding wires correspondingly on the plurality of redistribution layers in the recess and extending onto the at least one second substrate; and
providing at least one device substrate on the second side of the at least one first substrate.

12. The method as claimed in claim 11 , wherein the at least one device substrate comprises a plurality of first conducting pads therein, and the method further comprises forming a plurality of first conducting structures between the at least one first substrate and the at least one device substrate, such that the plurality of first conducting pads is electrically connected to the plurality of redistribution layers.

13. The method as claimed in claim 11 , wherein the at least one device substrate is a chip.

14. The method as claimed in claim 11 , wherein the at least one first substrate is a chip or an interposer.

15. The method as claimed in claim 11 , wherein the at least one second substrate is a chip, an interposer or a circuit board.

16. The method as claimed in claim 11 , further comprising providing a third substrate on the first side of the at least one first substrate, wherein the at least one second substrate is located between the at least one first substrate and the third substrate.

17. The method as claimed in claim 16 , wherein the third substrate comprises a plurality of second conducting pads, and the method further comprises forming a plurality of second conducting structures between the at least one second substrate and the third substrate, such that the plurality of second conducting pads is electrically connected to the bonding wires.

18. The method as claimed in claim 16 , wherein the third substrate is a chip, an interposer or a circuit board.

19. The method as claimed in claim 11 , wherein at least two of the plurality of redistribution layers have different widths and/or lengths as viewed from a top view perspective.

20. The method as claimed in claim 11 , wherein the expanded portions have different sizes and/or shapes.

21. The method as claimed in claim 11 , wherein at least two of the plurality of redistribution layers have the same width and/or length as viewed from a top view perspective.

22. The method as claimed in claim 11 , wherein the expanded portions have the same size and/or shape.

23. The stacked chip package as claimed in claim 1 , wherein at least two of the plurality of redistribution layers have the same width and/or length as viewed from a top view perspective.

24. The stacked chip package as claimed in claim 1 , wherein the expanded portions have the same size and/or shape.

Assignees

• Xintec Inc

Inventors

• Ho Yen-Shih
• Ho Chih-Wei
• Liu Tsang-Yu

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title