Semiconductor device

Patent metadata

Field	Value
Publication number	US-10347552-B2
Application number	US-201815879610-A
Country	US
Kind code	B2
Filing date	Jan 25, 2018
Priority date	Dec 24, 2014
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a wiring substrate;
an interposer mounted on a first surface of the wiring substrate;
a first semiconductor component having a first main surface, and a plurality of first electrodes disposed on the first main surface, the first semiconductor component being mounted on the interposer;
a second semiconductor component having a second main surface and a plurality of second electrodes formed on the second main surface, the second semiconductor component being mounted on the interposer and controlling the first semiconductor component; and
a plurality of external terminals formed on a second surface of the wiring substrate, which is opposite to the first surface,
wherein the interposer includes a base member made of a semiconductor material as a base material and a plurality of wiring layers arranged on a main surface of the base member,
wherein the first semiconductor component and the second semiconductor component are electrically connected to each other via the plurality of wiring layers,
wherein the plurality of wiring layers include a first wiring layer, a second wiring layer spaced farther away from the main surface of the base member than the first wiring layer, a third wiring layer spaced farther away from the main surface of the base member than the second wiring layer, and a fourth wiring layer spaced farther away from the main surface of the base member than the third wiring layer,
wherein a plurality of first electrode pads and a plurality of second electrode pads are formed in the fourth wiring layer of the interposer,
wherein the plurality of first electrodes of the first semiconductor component are electrically connected with the plurality of first electrode pads of the interposer,
wherein the plurality of second electrodes of the second semiconductor component are electrically connected with the plurality of second electrode pads of the interposer,
wherein, in a first region of the interposer which, in plan view, is sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a plurality of reference potential wirings in the third wiring layer, the plurality of reference potential wirings constituting a part of a transmission path of a reference potential, is higher than a ratio of a plurality of reference potential wirings in the first wiring layer,
wherein, in the first region of the interposer in plan view, a plurality of signal wirings are formed in the second wiring layer, and
wherein the first semiconductor component and the second semiconductor component are arranged next to each other.

2. The semiconductor device according to claim 1 ,
wherein the base member is a silicon substrate.

3. The semiconductor device according to claim 2 ,
wherein the part of the transmission path of the reference potential constituted by the plurality of reference potential wirings of the third wiring layer includes a plurality of metal patterns between which a clearance is formed, and
wherein an insulating layer is embedded in the clearance of the plurality of metal patterns.

4. The semiconductor device according to claim 3 ,
wherein, in the first region of the interposer in plan view, each of the plurality of signal wirings arranged in the second wiring layer are arranged between the plurality of reference potential wirings, which constitute a part of a transmission path of a reference potential, in the second wiring layer.

5. The semiconductor device according to claim 4 ,
wherein the reference potential wirings formed in the third wiring layer has a mesh shape in plan view.

6. The semiconductor device according to claim 2 ,
wherein the interposer is provided with a plurality of through electrodes which pass through the silicon substrate in a thickness direction, and
wherein each of the plurality of through electrodes is a conductive path which is formed by embedding a conductor in a through hole formed to pass through the silicon substrate in a thickness direction.

7. The semiconductor device according to claim 6 ,
wherein each of the plurality of through electrodes has one end connected to a rear surface electrode formed on a rear surface of the interposer and another end connected to a wiring of the plurality of wiring layers of the interposer.

8. The semiconductor device according to claim 6 ,
wherein each of the plurality of external terminals is a solder ball.

9. The semiconductor device according to claim 1 ,
wherein the fourth wiring layer is covered over a passivation film, and
wherein a part of each of the plurality of the first and second electrode pads is exposed from the passivation film.

10. The semiconductor device according to claim 1 ,
wherein a thickness of a wiring of the plurality of wiring layers of the interposer is smaller than a thickness of a wiring of the wiring substrate in a thickness direction of the interposer.

11. The semiconductor device according to claim 1 ,
wherein the plurality of first electrode pads of the interposer and the plurality of second electrode pads of the interposer are electrically connected to each other via a plurality of wirings in the third wiring layer of the interposer.

12. The semiconductor device according to claim 1 ,
wherein the plurality of wirings in the third wiring layer of the interposer are the plurality of reference potential wirings.

13. A semiconductor device comprising:
a wiring substrate;
an interposer mounted on a first surface of the wiring substrate;
a first semiconductor component having a first main surface and a plurality of first electrodes on the first main surface, the first semiconductor component being mounted on the interposer;
a second semiconductor component having a second main surface and a plurality of second electrodes formed on the second main surface, the second semiconductor being mounted on the interposer and controlling the first semiconductor component; and
a plurality of external terminals formed on a second surface of the wiring substrate, the second surface of the wiring substrate being opposite to the first surface,
wherein the first semiconductor component and the second semiconductor component are arranged next to each other,
wherein the interposer includes a base member made of a semiconductor material as a base material and a plurality of wiring layers arranged on a main surface of the base member,
wherein the plurality of wiring of wiring layers include a first wiring layer, a second wiring layer spaced father away from the main surface of the bade member then the first wiring layer, a third wiring layer spaced farther away from the main surface of the bade member than the second wiring layer, and a fourth wiring layer spaced farther away from the main surface of the base member than the third wiring later,
wherein, in a first region of the interposer which, in plan view, is sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a plurality of reference potential wirings in the third wiring layer, the plurality of reference potential wirings constituting a part of a transmission path of a reference potential, is higher than a ratio of a plurality of reference potential wirings in the first wiring layer.

Assignees

• Renesas Electronics Corp

Inventors

• Oikawa Ryuichi
• Ochiai Toshihiko
• Kariyazaki Shuuichi
• Kayashima Yuji
• Kida Tsuyoshi

Classifications

• H10W90/752

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W44/223

  Differential pair signal lines · CPC title