Integrated circuit structure including power rail and tapping wire with method of forming same

Patent metadata

Field	Value
Publication number	US-10347546-B2
Application number	US-201615389632-A
Country	US
Kind code	B2
Filing date	Dec 23, 2016
Priority date	Dec 23, 2016
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

The disclosure relates to integrated circuit (IC) structures with substantially T-shaped wires, and methods of forming the same. An IC structure according to the present disclosure can include a first substantially T-shaped wire including a first portion extending in a first direction, and a second portion extending in a second direction substantially perpendicular to the first direction; an insulator laterally abutting the first substantially T-shaped wire at an end of the first portion, opposite the second portion; and a pair of gates each extending in the first direction and laterally abutting opposing sidewalls of the insulator and the first portion of the substantially T-shaped wire.

First claim

What is claimed is:

1. An integrated circuit (IC) structure, comprising:
a first conductive region including a first tapping wire extending in a first direction, and a first power rail extending in a second direction substantially perpendicular to the first direction;
an insulator directly laterally abutting the first conductive region at a first end of the first tapping wire on a same level of the IC structure, wherein the first power rail directly laterally abuts a second, opposite end of the first tapping wire on the same level of the IC structure, wherein the insulator is positioned laterally between the first tapping wire and a second tapping wire, and positioned on at least one semiconductor fin;
a pair of gates each extending in the first direction and laterally abutting opposing sidewalls of the insulator and the first tapping wire of the first conductive region;
a second conductive region extending in the first direction and positioned on the at least one semiconductor fin and having a first sidewall laterally abutting one of the pair of gates;
an additional gate extending in the first direction and laterally abutting a second sidewall of the second conductive region opposite the first sidewall; and
a gate spacer extending continuously in the second direction from an end of one of the pair of gates to an end of the additional gate, wherein the gate spacer is positioned directly laterally between the first power rail of the first conductive region and each of: one of the pair of gates, the second conductive region, and the additional gate.

2. The IC structure of claim 1 , wherein the first power rail and the first tapping wire of the first conductive region define a T-shape.

3. The IC structure of claim 1 , further comprising a buried insulator layer underlying each of the pair of gates, the insulator, the first conductive region, the second conductive region, the additional gate, and the gate spacer, wherein the first power rail is located on the same level of the IC structure as the pair of gates.

4. The IC structure of claim 1 , wherein the first conductive region comprises tungsten (W).

5. The IC structure of claim 1 , wherein the first tapping wire of the first conductive region is structurally continuous with the first power rail of the first conductive region.

6. The IC structure of claim 1 , wherein a lateral thickness of the first power rail in the first direction is between approximately eight nanometers (nm) and approximately ten nm.

7. The IC structure of claim 1 , wherein the first power rail of the first conductive region is positioned laterally between one of the pair of gates, and an adjacent gate on the same level of the IC structure.

8. An integrated circuit (IC) structure, comprising:
a set of gates positioned over a buried insulator layer and each extending in a longitudinal direction, wherein the set of gates includes a first longitudinal trench between a first gate and a second gate of the set of gates, and a second longitudinal trench between the second gate and a third gate of the set of gates;
a first conductive region including:
a first power rail having a latitudinal orientation and positioned at a first longitudinal end of each of the set of gates, and
a first tapping wire structurally continuous with the first power rail and positioned within the first longitudinal trench, directly between the first gate and the second gate of the set of gates;

an insulator positioned on a semiconductor fin and directly laterally abutting the first conductive region within the first longitudinal trench at a first end of the first tapping wire on a same level of the IC structure, wherein the first power rail directly laterally abuts a second, opposite end of the first tapping wire on the same level of the IC structure, and wherein the first power rail is located on the same level of the IC structure as the set of gates;
a second conductive region positioned on the semiconductor fin and within the second longitudinal trench between the second gate and the third gate of the set of gates; and
a gate spacer positioned at a longitudinal end of the second gate and the third gate, having the latitudinal orientation, and extending continuously alongside the longitudinal end of the second gate and the third gate, and a longitudinal end of the second conductive region, wherein the gate spacer is positioned directly laterally between the first power rail of the first conductive region and each of: the second gate, the second conductive region, and the third gate.

9. The IC structure of claim 8 , wherein the first conductive region defines a T-shape.

10. The IC structure of claim 8 , wherein the first conductive region includes tungsten (W).

11. The IC structure of claim 10 , wherein the second conductive region comprises one of copper (Cu), aluminum (Al), or cobalt (Co).

12. The IC structure of claim 8 , wherein the first power rail of the first conductive region is positioned laterally between one of the pair of gates, and a longitudinally adjacent gate on the same level of the IC structure.

13. An integrated circuit (IC) structure, comprising:
a set of gates positioned over a buried insulator layer and each extending in a longitudinal direction, wherein the set of gates includes a first longitudinal trench between a first gate and a second gate of the set of gates, and a second longitudinal trench between the second gate and a third gate of the set of gates;
a first conductive region including:
a first power rail having a latitudinal orientation and positioned at a first longitudinal end of each of the set of gates, and
a first tapping wire structurally continuous with the first power rail and positioned within the first longitudinal trench, directly between the first gate and the second gate of the set of gates;

an insulator positioned on a semiconductor fin and directly laterally abutting the first conductive region within the first longitudinal trench at a first end of the first tapping wire on a same level of the IC structure, wherein the first power rail directly laterally abuts a second, opposite end of the first tapping wire on the same level of the IC structure, and wherein the first power rail is located on the same level of the IC structure as the set of gates;
a second conductive region including:
a second power rail having a latitudinal orientation and positioned at a second longitudinal end of each of the set of gates opposite the first longitudinal end, and
a second tapping wire structurally continuous with the second power rail and positioned within the first longitudinal trench, directly between the first gate and the second gate of the set of gates, wherein the insulator is positioned laterally between the first and second tapping wires;

a third conductive region positioned on the semiconductor fin and within the second longitudinal trench between the second gate and the third gate of the set of gates; and
a gate spacer positioned at a longitudinal end of the second gate and the third gate, having the latitudinal orientation, and extending continuously alongside the longitudinal end of the second gate and the third gate, and a longitudinal end of the third conductive region, wherein the gate spacer is positioned directly laterally between the first conductive region and each of: the second gate, the third conductive region, and the third gate.

14. The IC structure of claim 13 , wherein each of the first conductive region, the second conductive region, and the third conductive region have a same height above the buried insulator layer.

15. The IC structure of claim 13 , w

Assignees

• Globalfoundries Inc

Inventors

• Zeng Jia
• Wang Wenhui
• Zhu Xuelian
• Kye Jongwook

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title