Read voltage calibration based on host IO operations

Patent metadata

Field	Value
Publication number	US-10347344-B2
Application number	US-201715689747-A
Country	US
Kind code	B2
Filing date	Aug 29, 2017
Priority date	Aug 29, 2017
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.

First claim

What is claimed is:

1. A memory device, comprising:
a NAND memory array having groups of multiple blocks of memory cells; and
a memory controller operably coupled to the NAND memory array, the memory controller to perform operations comprising:
monitoring read operations occurring to a respective; block of the NAND memory array;
identifying, based at least in part on the read operations occurring to the respective block, a condition to trigger a read level calibration; and
performing, in response to the identified condition, the read level calibration based on a threshold voltage level of a respective group of multiple blocks hosting the respective block, wherein the read level calibration is performed based at least in part on a threshold voltage to read the respective block.

2. The memory device of claim 1 , wherein monitoring the read operations includes tracking a number of reads to the respective block, and wherein the condition to trigger the read level calibration is identified, at least in part, based on the number of reads occurring to the respective block exceeding a determined number of reads.

3. The memory device of claim 2 , the operations of the memory controller further comprising monitoring erase operations occurring to the respective block, wherein the condition to trigger the read level calibration is further identified based on a number of erases to the respective block exceeding a determined number of erases.

4. The memory device of claim 3 , wherein the number of reads to the respective block is tracked in a first counter maintained in a memory accessible by the memory controller, wherein the number of erases to the respective block is tracked in a second counter maintained in the memory accessible by the memory controller, and wherein an erase occurring to the respective block resets the first counter.

5. The memory device of claim 1 , wherein monitoring the read operations includes tracking a number of reads to the respective group of multiple blocks hosting the respective block, and wherein the condition to trigger the read level calibration is identified, at least in part, based on the number of reads occurring to the respective group of multiple blocks exceeding a determined number of reads.

6. The memory device of claim 1 , wherein the condition to trigger the read level calibration is further based in part on a raw bit error rate (RBER) of read operations occurring to at least the respective block of the memory array.

7. The memory device of claim 1 , wherein performing the read level calibration includes performing a sampling of the threshold voltage to read the respective block in addition to threshold voltages to read other blocks located among the groups of multiple blocks in the memory array.

8. The memory device of claim 7 , wherein other blocks in the memory array included in the sampling are identified within the memory array based on a number of read operations performed among respective blocks of the other blocks.

9. The memory device of claim 7 , wherein other blocks in the memory array included in the sampling are identified within the memory array based on at least one of: random sampling of the other blocks in the memory array, sampling of the other blocks in the memory array based on data age, or sampling of the other blocks in the memory array based on raw hit error rate (RBER) corresponding to the other blocks.

10. The memory device of claim 1 , wherein the read operations to the respective block are monitored by monitoring read operations to one or more portions of the respective block.

11. The memory device of claim 10 , wherein the monitored portions of the respective block include pages of the respective block.

12. The memory device of claim 1 , wherein the memory device is operably coupled to a host, wherein the host initiates commands to perform respective reads among the multiple blocks in the memory array, and wherein the respective reads include multiple reads occurring to a logical block address corresponding to a page located within the respective block.

13. The memory device of claim 1 , wherein the read level calibration updates one or more read voltage levels used to read one or more pages of the respective block in subsequent read operations occurring to the one or more pages of the respective block.

14. The memory device of claim 1 , wherein the blocks of memory cells of the memory array include at least one of: single-level cell (SLC), multi-layer cell (MLC), triple-layer cell (TLC), or quad-layer cell (QLC) NAND memory cells.

15. The memory device of claim 1 , wherein the memory array is arranged into a stack of three-dimensional (3D) NAND dies, and wherein the respective group of multiple blocks hosting the respective block corresponds to a group of blocks provided by a respective die in the stack of 3D NAND dies.

16. A method for optimizing voltage read level calibration in a memory device, the method comprising a plurality of operations performed by a memory controller of a NAND memory array, and the memory array having groups of multiple blocks of memory cells, with the operations comprising:
monitoring read commands issued to a respective block of the AND memory array;
identifying, based at least in part on the read commands issued to the respective block, a condition to trigger a read level calibration; and
performing, in response to the identified condition, the read level calibration based on a threshold voltage level of a respective group of multiple blocks hosting the respective block, wherein the read level calibration is performed based at least in part on a threshold voltage to read the respective block.

17. The method of claim 16 , wherein monitoring the read commands includes tracking a number of reads to the respective block, and wherein the condition to trigger the read level calibration is identified, at least in part, based on the number of reads occurring to the respective block exceeding a determined number of reads.

18. The method of claim 17 , the operations of the memory controller further comprising:
monitoring erase commands occurring to the respective block, wherein the condition to trigger the read level calibration is further identified based on a number of erases to the respective block exceeding a determined number of erases;
wherein the number of reads to the respective block is tracked in a first counter, wherein the number of erases to the respective block is tracked in a second counter, and wherein an erase occurring to the respective block resets the first counter.

19. The method of claim 16 , wherein monitoring the read operations includes tracking a number of reads to the respective group of multiple blocks hosting the respective block, and wherein the condition to trigger the read level calibration is identified, at least in part, based on the number of reads occurring to the respective group of multiple blocks exceeding a determined number of reads.

20. The method of claim 16 , wherein the condition to trigger the read level calibration is further based in part on a raw bit error rate (RBER) of read operations occurring to at least the respective block of the memory array.

21. The method of claim 16 , wherein performing the read level calibration includes performing a sampling of the threshold voltage to read the respective block in addition to threshold voltages to read other blocks located among the groups of multiple blocks in the memory array.

22. The method of claim 21 , wh

Assignees

• Micron Technology Inc

Inventors

• Malshe Ashutosh
• Muchherla Kishore Kumar
• Singidi Harish
• Feeley Peter Sean
• Ratnam Sampath
• Tanpairoj Kulachet
• Luo Ting

Classifications

• G11C2207/2254

  Calibration · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C29/021

  in voltage or current generators · CPC title

• G11C16/349

  Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles · CPC title

• G11C16/28

  using differential sensing or reference cells, e.g. dummy cells · CPC title