Method for determining system reliability of a logic circuit

Patent metadata

Field	Value
Publication number	US-10346570-B2
Application number	US-201515328321-A
Country	US
Kind code	B2
Filing date	Jul 22, 2015
Priority date	Jul 23, 2014
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

A method for determining system reliability of a logic circuit, wherein a functional component model for design/simulation of a circuit model of the logic circuit is created, where functional components model are expanded by adding an associated power model, a temperature model, and a reliability, where the logic circuit is constructed with expanded model components and, based on simulation of the logic circuit aided by the constructed circuit model, a functional, a power-dependent, and a temperature-dependent behavior and a temperature-dependent failure rate are derived for each component in a component specific manner for a specified application case, and where in addition to the functional behavior, a power and temperature behavior and a total failure rate can be determined simply and dynamically, based on the derived data and dependent on temperature and simulation time for the logic circuit for the specified application case.

First claim

The invention claimed is:

1. A method for determining a system reliability of a logic circuit which is constructed out of a processor unit and individual components, a functional component model for design and simulation of a circuit model of the logic circuit being created for each component, the method comprising:
adding an associated power model, a temperature model based on the power model and a reliability model based on the temperature model for a respective individual component to expand the respective functional component model;
constructing the circuit model of the logic circuit via expanded component models;
deriving, based on a simulation of the logic circuit aided by the circuit model, a functional, a power-dependent, a temperature-dependent behavior and a temperature-dependent failure rate for the respective individual component in a component-specific manner for a specified application case; and
creating and operating the logic circuit based on the derived functional, power-dependent, temperature-dependent behavior and the temperature-dependent failure rate for the respective individual component in a component-specific manner for the specified application case.

2. The method as claimed in claim 1 , further comprising:
determining a model representing a total failure rate of the logic circuit based on the component-specific temperature-dependent failure rate for the specified application case.

3. The method as claimed in claim 1 , further comprising:
determining at least one of (i) a power behavior and (ii) a temperature behavior of the logic circuit is furthermore determined from at least one of (i) the power-dependent and (ii) temperature-dependent behavior of the respective individual components for the specified application case.

4. The method as claimed in claim 2 , further comprising:
determining at least one of (i) a power behavior and (ii) a temperature behavior of the logic circuit is furthermore determined from at least one of (i) the power-dependent and (ii) temperature-dependent behavior of the respective individual components for the specified application case.

5. The method as claimed in claim 1 , wherein ambient conditions are also taken into account alongside the component-specific temperature behavior to derive the component-specific temperature-dependent failure rate of the respective individual component.

6. The method as claimed in claim 2 , wherein ambient conditions are also taken into account alongside the component-specific temperature behavior to derive the component-specific temperature-dependent failure rate of the respective individual component.

7. The method as claimed in claim 3 , wherein ambient conditions are also taken into account alongside the component-specific temperature behavior to derive the component-specific temperature-dependent failure rate of the respective individual component.

8. The method as claimed in claim 1 , wherein a simulation time for the respective specified application case is taken into account during derivation of the component-specific temperature-dependent failure rates and also during determination of the total failure rate for the logic circuit.

9. The method as claimed in claim 1 , wherein the circuit model of the logic circuit is implemented as a High-Level Model.

10. The method as claimed in claim 1 , wherein the logic circuit comprises an integrated circuit.

11. The method as claimed in claim 1 , wherein the logic circuit comprises one of a field-programmable logic gate arrangement and a Field-Programmable Gate Array.

12. The method as claimed in claim 9 , wherein the High-Level Model comprises an Electronic-System Level model.

13. The method as claimed in claim 10 , wherein the integrated circuit comprises one of an Application-Specific Integrated Circuit and a System-on-Chip.

Assignees

• Siemens Ag Oesterreich

Inventors

• Cech Christian
• Fischer Bernhard
• Hinterstoisser Thomas
• Matschnig Martin

Classifications

• G06F11/076

  by exceeding a count or rate limit, e.g. word- or bit count limit · CPC title

• G06F2119/08

  Thermal analysis or thermal optimisation · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F11/24 Primary

  Marginal checking {or other specified testing methods not covered by G06F11/26, e.g. race tests} · CPC title

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title