Updating virtual machine memory by interrupt handler

US10346330B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10346330-B2
Application numberUS-201414167497-A
CountryUS
Kind codeB2
Filing dateJan 29, 2014
Priority dateJan 29, 2014
Publication dateJul 9, 2019
Grant dateJul 9, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Systems and methods for directly updating the virtual machine memory by interrupt handlers. An example method may comprise: receiving, by a computer system, an interrupt triggered by a physical device; receiving, by an interrupt handling routine, a data frame from the physical device; identifying a virtual machine to receive the interrupt; and responsive to determining that an active memory context on the computer system matches a memory context of the virtual machine, writing, by the interrupt handling routine, the data frame into a memory of the virtual machine.

First claim

Opening claim text (preview).

What is claimed is: 1. A method, comprising: receiving, by a processor of a host computer system, an interrupt triggered by a physical device; receiving, by an interrupt handling routine, a data frame from the physical device; identifying, by the processor, a paravirtualized input/output (I/O) device to receive the interrupt; responsive to determining that an active memory context associated with the processor matches a memory context of a virtual machine associated with the paravirtualized I/O device, writing the data frame into a memory of the virtual machine; and responsive to determining that a page fault has been triggered by the writing operation, queuing the data frame for processing by an I/O processing thread and waking up the I/O processing thread. 2. The method of claim 1 , wherein the physical device is provided by one of: a network interface card or a hard disk controller. 3. The method of claim 1 , further comprising: enabling page fault handling by the host computer system responsive to determining that no page fault has been triggered by the write operation. 4. The method of claim 1 , further comprising: responsive to determining that the active memory context associated with the processor does not match the memory context of the virtual machine, queuing the data frame for processing by the I/O processing thread. 5. A system comprising: a memory; and a processor, operatively coupled to the memory, to: receive an interrupt triggered by a physical device; receive, by an interrupt handling routine, a data frame from the physical device; identify a paravirtualized input/output (I/O) device to receive the interrupt; responsive to determining that an active memory context associated with the processor matches a memory context of a virtual machine associated with the paravirtualized I/O device, disable page fault handling by the virtual machine and write the data frame into a memory of the virtual machine; and responsive to determining that the active memory context associated with the processor does not match the memory context of the virtual machine, queue the data frame for processing by an I/O processing thread and wake up the I/O processing thread. 6. The system of claim 5 , wherein the physical device is provided by one of: a network interface card or a hard disk controller. 7. The system of claim 5 , wherein the processor is further to: enable page fault handling by the virtual machine responsive to determining that no page fault has been triggered by the write operation. 8. A computer-readable non-transitory storage medium comprising executable instructions that, when executed by a processor, cause the processor to: receive, by the processor, an interrupt triggered by a physical device; receive, by an interrupt handling routine, a data frame from the physical device; identify, by the processor, a paravirtualized input/output (I/O) device to receive the interrupt; responsive to determining that an active memory context associated with the processor matches a memory context of a virtual machine associated with the paravirtualized I/O device, write the data frame into a memory of the virtual machine; and responsive to determining that a page fault has been triggered by the writing operation, queue the data frame for processing by an I/O processing thread and wake up the I/O processing thread. 9. The computer-readable non-transitory storage medium of claim 8 , wherein the physical device is provided by one of: a network interface card or a hard disk controller. 10. The computer-readable non-transitory storage medium of claim 8 , further comprising executable instructions causing the processor to: enable page fault handling by the virtual machine responsive to determining that no page fault has been triggered by the write operation. 11. The computer-readable non-transitory storage medium of claim 8 , further comprising executable instructions causing the processor to: responsive to determining that the active memory context associated with the processor does not match the memory context of the virtual machine, queue the data frame for processing by the I/O processing thread. 12. The method of claim 1 , further comprising: notifying the virtual machine of the data frame. 13. The method of claim 1 , wherein the active memory context associated with the processor comprises a page table utilized for translating virtual addresses to physical addresses. 14. The method of claim 1 , wherein identifying the virtual machine comprises identifying a network interface card identified by a Media Access Control (MAC) address of the data frame. 15. The method of claim 1 , wherein writing the data frame into a memory of the virtual machine is performed by the interrupt handling routine. 16. The method of claim 1 , further comprising: responsive to determining that the active memory context associated with the processor matches the memory context of the virtual machine, disabling page fault handling by the virtual machine thus causing the host computer system to handle page faults. 17. The method of claim 1 , further comprising: responsive to determining that no page fault has been triggered by writing the data frame into the memory of the virtual machine, injecting an interrupt into a virtual processor associated with the virtual machine to notify the virtual machine of the data frame. 18. The computer-readable non-transitory storage medium of claim 8 , further comprising executable instructions to cause the processor to: responsive to determining that the active memory context associated with the processor matches the memory context of the virtual machine, disable page fault handling by the virtual machine. 19. The computer-readable non-transitory storage medium of claim 8 , further comprising executable instructions to cause the processor to: inject an interrupt into a virtual processor associated with the virtual machine to notify the virtual machine of the data frame. 20. The computer-readable non-transitory storage medium of claim 8 , wherein the active memory context comprises a page table utilized for translating virtual addresses to physical addresses.

Assignees

Inventors

Classifications

  • Interrupt packet, e.g. event · CPC title

  • by interrupt, e.g. masked · CPC title

  • Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455) · CPC title

  • the resource being a machine, e.g. CPUs, Servers, Terminals · CPC title

  • G06F13/34Primary

    with priority control · CPC title

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What does patent US10346330B2 cover?
Systems and methods for directly updating the virtual machine memory by interrupt handlers. An example method may comprise: receiving, by a computer system, an interrupt triggered by a physical device; receiving, by an interrupt handling routine, a data frame from the physical device; identifying a virtual machine to receive the interrupt; and responsive to determining that an active memory con…
Who is the assignee on this patent?
Red Hat Israel Ltd
What technology area does this patent fall under?
Primary CPC classification G06F13/34. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jul 09 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).