Phase-locked circuit with automatic calibration function and automatic calibration method thereof

Patent metadata

Field	Value
Publication number	US-10340924-B1
Application number	US-201816132566-A
Country	US
Kind code	B1
Filing date	Sep 17, 2018
Priority date	May 25, 2018
Publication date	Jul 2, 2019
Grant date	Jul 2, 2019

Abstract

A digital phase-locked loop with an automatic calibration function and an automatic calibration method thereof are provided. The digital phase-locked loop includes a frequency and phase detector, a calibration circuit, a frequency and phase locked circuit, and an oscillator circuit. The frequency and phase locked circuit outputs an initial control signal. The calibration circuit calibrates an initial frequency and outputs an initial calibration signal having a calibrated initial frequency when determining that the initial frequency does not fall within an allowable error calibration range. The frequency and phase locked circuit locks the calibrated initial frequency when determining that the calibrated initial frequency falls within a locked frequency range. The oscillator circuit outputs an oscillator signal according to the initial calibration signal and the initial control signal. Therefore, a resolution of the oscillator circuit can be improved by the automatic calibration of frequency drift caused by processes and environments.

First claim

What is claimed is:

1. A digital phase-locked loop with an automatic calibration function comprising:
a frequency and phase locked circuit configured to receive a calibration control signal from an external electronic device and output a corresponding initial control signal, wherein the frequency and phase locked circuit is configured to track a calibrated initial frequency and an initial phase of an initial calibration signal, and lock the calibrated initial frequency and the initial phase when the calibrated initial frequency falls within a locked calibration frequency range and the initial phase falls within a locked phase range, the frequency and phase locked circuit is configured to lock a divided frequency and a divided phase of a divided signal when determining that the divided frequency falls within a locked frequency range and the divided phase falls within the locked phase range;
a calibration circuit connected to the frequency and phase locked circuit, the calibration circuit being configured to store an allowable calibration error range, and calibrate the initial frequency to generate the calibrated initial frequency and output the initial calibration signal having the calibrated initial frequency when determining that an initial frequency of the initial control signal does not fall within the allowable calibration error range;
an oscillator circuit connected to the calibration circuit and the frequency and phase locked circuit, the oscillator circuit being configured to output an oscillator signal according to the initial calibration signal and the initial control signal;
a divider connected to the oscillator circuit and configured to receive a divisor instructing signal indicating a preset divisor value from an external electronic device, the divider being further configured to divide an oscillation frequency of the oscillator signal by the preset divisor value to generate the divided signal, the preset divisor value being associated with a ratio of a reference frequency and the oscillating frequency; and
a frequency and phase detector connected to the divider, the frequency and phase detector being configured to detect a frequency difference between the divided frequency and the reference frequency and a phase difference between the divided phase and a reference phase, and being configured to output the frequency difference and the phase difference to the frequency and phase locked circuit as a basis for determining that the divided frequency falls within the locked frequency range and the divided phase falls within the locked phase range.

2. The digital phase-locked loop of claim 1 , wherein the locked frequency range includes a coarse locked frequency range and a fine locked frequency range, the locked phase range includes a coarse locked phase range and a fine locked phase range, the frequency and phase-locked circuit including:
a coarse locking circuit connected to the frequency and phase detector and the oscillator circuit, wherein the coarse locking circuit is configured to store the coarse locked frequency range and the coarse locked phase range, the coarse locking circuit is configured to lock the calibrated initial frequency or the divided frequency when tracking that the calibrated initial frequency or the divided frequency falls within the coarse locked frequency range, lock the initial phase or the divided phase when tracking that the initial phase or the divided phase falls within the coarse locked phase range, and output a corresponding coarse locking signal; and
a fine locking circuit connected to the frequency and phase detector and the oscillator circuit, wherein the fine locking circuit is configured to store the fine locked phase range and the fine locked phase range, the fine locking circuit is configured to lock the calibrated initial frequency or the divided frequency when tracking that the calibrated initial frequency or the divided frequency falls within the fine locked frequency range, and the fine locking circuit is configured to lock the initial calibration phase or the divided phase when tracking that the initial calibration phase or the divided phase falls within the fine locked phase range, and output a corresponding fine locking signal.

3. The digital phase-locked loop of claim 2 , further comprising: an encoder connected to the coarse locking circuit, the fine locking circuit and the oscillator circuit, wherein the encoder is configured to encode the coarse locking signal and the fine locking signal to output a lock control signal to the oscillator circuit, the oscillator circuit is configured to output another oscillator signal according to the lock control signal.

4. The digital phase-locked loop of claim 1 , wherein the frequency and phase detector is configured to detect a divided frequency difference between the divided frequency of the divided signal and the reference frequency;
the calibration circuit is configured to calibrate the divided frequency when determining that the divided frequency does not fall within the allowable calibration error range according to the divided frequency difference, and output a divided calibration signal including a calibrated divided frequency;
the frequency and phase locked circuit is configured to lock the calibrated divided frequency and output a corresponding lock control signal when determining that the calibrated divided frequency falls within the locked frequency range;
the oscillator circuit is configured to output another oscillator signal according to the lock control signal and the divided calibration signal.

5. An automatic calibration method for a digital phase-locked loop with an automatic calibration function, comprising the following steps:
(a) outputting an initial control signal from a frequency and phase locked circuit;
(b) calibrating an initial frequency to generate an calibrated initial frequency and outputting an initial calibration signal having the calibrated initial frequency by a calibration circuit when determining that the initial frequency of the initial control signal does not fall within an allowable calibration error range by the calibration circuit;
(c) tracking whether the calibrated initial frequency falls within a locked calibration frequency range or not by the frequency and phase locked circuit; when the calibrated initial frequency does not fall within the locked calibration frequency range, performing step (b);
when the calibrated initial frequency falls within the locked calibration frequency range, locking the calibrated initial frequency by the frequency and phase locked circuit and then performing step (d);
(d) outputting an oscillator signal according to the initial calibration signal and the initial control signal by an oscillator circuit;
(e) dividing an oscillation frequency of the oscillator signal by a preset divisor value to generate a divided signal by a divider;
(f) detecting a frequency difference between a divided frequency of the divided signal and a reference frequency, and a phase difference between a divided phase of the divided signal and a reference phase by the frequency and phase detector;
(g) tracking whether the divided frequency falls within a locked frequency range according to the frequency difference or not by the frequency and phase locked circuit; when the divided frequency does not fall within the locked frequency range, continuing to track the divided frequency; when the divided frequency falls within the locked frequency range, locking the divided frequency by the frequency and phase locked circuit and then performing step (h);
(h) tracking whether the divided phase falls within a locked phase range according to the phase difference or not by the frequency and phase locked circuit; when the divided phase does not fall within the locked phase range, contin

Assignees

• Anpec Electronics Corp

Inventors

• Chen jing-min

Classifications

• H03L7/0991

  the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider (H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814) · CPC title

• H03L2207/06

  Phase locked loops with a controlled oscillator having at least two frequency control terminals · CPC title

• H03L7/104

  using an additional signal from outside the loop for setting or controlling a parameter in the loop (H03L7/107, H03L7/12 take precedence) · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/103 Primary

  the additional signal being a digital signal · CPC title