Amplifier

Patent metadata

Field	Value
Publication number	US-10340865-B2
Application number	US-201816106963-A
Country	US
Kind code	B2
Filing date	Aug 21, 2018
Priority date	Mar 23, 2017
Publication date	Jul 2, 2019
Grant date	Jul 2, 2019

Abstract

An amplifier of an embodiment includes: a plurality of input transistors of a plurality of differential pairs; a plurality of first resistance circuits mutually connecting respective sources of the input transistors corresponding to the differential pairs and mutually connecting the respective sources and reference potential points; a plurality of second resistance circuits being connected between the respective sources of the plurality of input transistors and the reference potential points, respectively; and a control circuit configured to generate a control signal controlling whether or not to electrically connect the plurality of first resistance circuits and the plurality of second resistance circuits to the respective sources of the input transistors.

First claim

What is claimed is:

1. An amplifier comprising:
a pair of current sources;
a plurality of first differential input transistors comprising:
a first plurality of transistors having first ends connected to one of the pair of current sources, and control ends to which positive a phase input signal is inputted, and
a second plurality of transistors respectively constituting differential pairs with the first plurality of transistors, the second plurality of transistors having first ends connected to the other of the pair of current sources, and control ends to which negative a phase input signal is inputted;

a plurality of second differential input transistors comprising:
a third plurality of transistors having first ends connected to one of the pair of current sources, and control ends to which the positive phase input signal is inputted, and
a fourth plurality of transistors respectively constituting differential pairs with the third first plurality of transistors, the fourth plurality of transistors having first ends connected to the other of the pair of current sources, and control ends to which the negative phase input signal is inputted, the number of the second plurality of differential input transistors being the same as the number of the number of the first differential input transistors;
a plurality of resistance adjusting transistors having first ends respectively connected to second ends of the plurality of first differential input transistors, second ends connected to reference potential points, and control ends to which control signals are inputted;
a plurality of wirings that connect the second ends of the plurality of first differential input transistors that constitute the differential pairs of the plurality of first differential input transistors;

a plurality of linearity improving transistors having first ends respectively connected to second ends of the plurality of second differential input transistors, second ends connected to the reference potential points, and control ends to which the control signals are inputted; and
a control circuit configured to change a linearity improvement effect while controlling an operating point, by supplying the control signals to the control ends of the plurality of resistance adjusting transistors and to the control ends of the plurality of linearity improving transistors.

2. The amplifier according to claim 1 , wherein the control circuit generates a control signal for causing a sum of resistance values of the resistance adjusting transistors that are turned on by the control signals and a sum of resistance values of the linearity improving transistors that are turned on by the control signals to be constant.

3. The amplifier according to claim 2 , wherein the control circuit generates a control signal for causing a sum of gate widths of the resistance adjusting transistors that are turned on by the control signals and a sum of gate widths of the linearity improving transistors that are turned on by the control signals to be constant.

4. The amplifier according to claim 1 , wherein the plurality of resistance adjusting transistors and the plurality of linearity improving transistors comprise a set of transistors having mutually same resistance values, and the control circuit outputs a control signal for complementarily turning on the set of transistors having the same resistance values.

5. The amplifier according to claim 1 , wherein the resistance values of the plurality of resistance adjusting transistors are set to a predetermined rate, and the resistance values of the plurality of linearity improving transistors are set to be same as the resistance values of the plurality of resistance adjusting transistors.

Assignees

• Toshiba Kk
• Toshiba Electronic Devices & Storage Corp

Inventors

• Shirane Atsushi
• Ito Rui
• Mitomo Toshiya

Classifications

• H03G1/0029

  using field-effect transistors [FET] · CPC title

• H03F2203/45352

  the AAC comprising a combination of a plurality of transistors, e.g. Darlington coupled transistors · CPC title

• H03F3/45197

  Pl types (H03F3/45224, H03F3/45251 take precedence) · CPC title

• H03G1/0088

  using discontinuously variable devices, e.g. switch-operated · CPC title

• H03F3/45179

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title