Receiver having a wide common mode input range

Patent metadata

Field	Value
Publication number	US-9306509-B2
Application number	US-201213560944-A
Country	US
Kind code	B2
Filing date	Jul 27, 2012
Priority date	Jul 27, 2012
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

In one embodiment, a differential amplifier is provided. Gates of a first differential pair of transistors, of a first conductivity type, and a second pair or transistors, of a second conductivity type are coupled to first and second input terminals of the differential amplifier. A first pair of adjustable current sources are configured to adjust respective tail currents of the first differential pair of transistors in response to a first bias current control signal. A second pair of adjustable current sources are configured to adjust respective tail currents of the second differential pair of transistors in response to the first bias current control signal. A third pair of adjustable current sources are configured to adjust respective currents through the second differential pair of transistors in response to a second bias current control signal.

First claim

What is claimed is:

1. A differential amplifier, comprising:
first and second input terminals;
a first differential pair of transistors having a first conductivity type and gates coupled to the first and second input terminals, respectively;
a second differential pair of transistors having a second conductivity type and gates coupled to the first and second input terminals, respectively;
a first pair of adjustable current sources coupled to the first differential pair of transistors and configured to adjust respective tail currents of the first differential pair of transistors in response to a first bias current control signal;
a second pair of adjustable current sources coupled to the second differential pair of transistors and configured to adjust respective tail currents of the second differential pair of transistors in response to the first bias current control signal; and
a third pair of adjustable current sources coupled to the second differential pair of transistors and configured to adjust respective currents through the second differential pair of transistors in response to a second bias current control signal.

2. The differential amplifier of claim 1 , further comprising a constant transconductance bias generator coupled to the first and second pairs of adjustable current sources and configured to generate the first bias current control signal.

3. The differential amplifier of claim 1 , further comprising, a bias generation circuit coupled to the third pair of adjustable current sources and configured to generate the second bias current control signal from the first bias current control signal.

4. The differential amplifier of claim 1 , wherein:
a first transistor of the first differential pair of transistors has a drain and a source, the drain coupled to receive a current from a first current source and coupled to a first output terminal of the differential amplifier, and the source coupled to a first one of the first pair of adjustable current sources;
a second transistor of the first differential pair of transistors has a drain and a source, the drain coupled to receive current from a second current source and coupled to a second output terminal of the differential amplifier, and the source coupled to a second one of the first pair of adjustable current sources;
a first transistor of the second differential pair of transistors has a source coupled to a first one of the third pair of adjustable current sources and has a drain coupled to a first one of the second pair of adjustable current sources; and
a second transistor of the second differential pair of transistors has a source coupled to a second one of the third pair of adjustable current sources and has a drain coupled to a second one of the second pair of adjustable current sources.

5. The differential amplifier of claim 4 , further comprising:
a first MOSFET coupled between the drain of the first transistor of the second differential pair of transistors and the first output terminal of the differential amplifier, the first MOSFET having a gate coupled to receive a third bias current control signal; and
a second MOSFET coupled between the drain of the second transistor of the second differential pair of transistors and the second output terminal of the differential amplifier, the second MOSFET having a gate coupled to receive a third bias current control signal.

6. The differential amplifier of claim 4 , further comprising a control circuit configured to:
while operating in a first mode, enable operation of the first differential pair of transistors and disable operation of the second differential pair of transistors; and
while operating in a second mode, enable operation of the second differential pair of transistors and disable operation of the first differential pair of transistors.

7. The differential amplifier of claim 6 , wherein the control circuit is configured to:
perform the disabling of operation of the first differential pair of transistors by disconnecting the first bias current control signal from the first pair of adjustable current sources; and
perform the disabling of operation of the second differential pair of transistors by disconnecting the first bias current control signal from the third pair of adjustable current sources, disconnecting the second bias current control signal from the second pair of adjustable current sources, and disconnecting the third bias current control signal from the gates of the first and second MOSFETs.

8. The differential amplifier of claim 4 , further comprising:
a first programmable resistor coupled between the sources of the first differential pair of transistors; and
a second programmable resistor coupled between the sources of the second differential pair of transistors, the first and second programmable resistors configured to adjust gain and frequency response of the differential amplifier in response to a gain control signal.

9. The differential amplifier of claim 4 , further comprising:
a zero frequency adjustment circuit coupled to the first and second differential pairs of transistors, the zero frequency adjustment circuit configured to adjust a zero frequency of the differential amplifier in response to a frequency control signal.

10. The differential amplifier of claim 9 , wherein the zero frequency adjustment circuit includes first, second, third, and fourth, programmable capacitors coupled between respective sources of the first and second differential pairs of transistors and a ground voltage.

11. The differential amplifier of claim 1 , further comprising a termination resistor circuit coupled between the first and second input terminals.

12. The differential amplifier of claim 1 , further comprising an electrostatic discharge circuit coupled to the first and second input terminals.

13. An analog front-end circuit, comprising:
a first electrostatic discharge circuit having inputs for receiving a differential signal from a transmission medium;
termination resistors coupled to differential outputs of the first electrostatic discharge circuit and configured to match the impedance of the analog front end to impedance of the transmission medium;
an equalizer circuit including a first differential amplifier circuit coupled to receive the differential signal from differential outputs of the termination resistors, the first differential amplifier circuit including:
an NMOS differential pair having inputs connected to the differential outputs of the termination resistors, the NMOS differential pair and configured to receive and amplify the differential signal using a high common mode voltage, the NMOS differential pair biased during operation by a first pair of adjustable current sources in response to a first bias current control signal;
a PMOS differential pair having inputs connected to the differential outputs of the termination resistors, the PMOS differential pair configured to receive and amplify the differential signal using a low common mode voltage, the PMOS differential pair biased during operation by a second pair of adjustable current sources in response to the first bias current control signal and by a third pair of adjustable current sources in response to a second bias current control signal; and
a control circuit configured to:
when operating in a low common mode, enable operation of the PMOS differential pair and disable operation of the NMOS differential pair; and
when operating in a high common mode, enable operation of the NMOS differential pair and disable operation of the PMOS differential pair.

14. The analog front-end circuit of claim 13 , wherein the equaliz

Assignees

• Lim Siok Wei
• Hsieh Cheng-Hsiang
• Savoj Jafar
• Xilinx Inc

Inventors

• Lim Siok Wei
• Hsieh Cheng-Hsiang
• Savoj Jafar

Classifications

• H03F2203/45092

  Two current sources bias one set of two common base transistors cascaded with two other common base transistors, the common base transistors being driven complementary · CPC title

• H03F3/45224

  Complementary Pl types having parallel inputs and being supplied in parallel · CPC title

• H04L27/0002

  analog front ends; means for connecting modulators, demodulators or transceivers to a transmission line (duplex arrangements H04L5/143) · CPC title

• H03F2203/45091

  Two complementary type differential amplifiers are paralleled, e.g. one of the p-type and one of the n-type · CPC title

• H03F2203/45494

  the CSC comprising one or more potentiometers · CPC title