Light emitting diode chip and fabrication method

Patent metadata

Field	Value
Publication number	US-10340469-B2
Application number	US-201715853890-A
Country	US
Kind code	B2
Filing date	Dec 25, 2017
Priority date	Dec 4, 2015
Publication date	Jul 2, 2019
Grant date	Jul 2, 2019

Abstract

A light-emitting diode chip includes an electrical connection layer is arranged over the light-emitting surface of the light-emitting epitaxial laminated layer, which is not connected with isolation of the dielectric layer. After CMP treatment, the flat surface is plated with a transparent current spreading layer, which reduces horizontal conduction resistance of the transparent current spreading layer and replaces the metal spreading finger for horizontal conduction.

First claim

The invention claimed is:

1. A fabrication method of a light-emitting diode chip, comprising:
1) providing a light-emitting epitaxial laminated layer, comprising a first-type semiconductor layer, a second-type semiconductor layer and an active layer between them, which has two surfaces opposite to each other, wherein, the second surface is the light-emitting surface;
2) fabricating a first electrical connection layer over the first surface of the light-emitting epitaxial laminated layer, which is composed of first geometric pattern arrays;
3) fabricating a second electrical connection layer over the second surface of the light-emitting epitaxial laminated layer, which is composed of second geometric pattern arrays;
4) fabricating a transparent current spreading layer over the surface of the second electrical connection layer; when external power is connected, the horizontal resistance of current passing through the transparent current spreading layer is less than that passing through the first electrical connection layer;
wherein step 3) comprises evaporating a second electrical connection layer over the second surface of the light-emitting epitaxial laminated layer; evaporating a second dielectric material layer over the surface; etching the second electrical connection layer region to expose the second electrical connection layer; and flattening the surface of the second connection layer through chemical mechanical polishing.

2. The fabrication method of claim 1 , further comprising step 5):
fabricating a first electrode over the transparent current spreading layer, in which, when current is injected to the first electrode and conducted to the transparent current spreading layer, it is horizontally conducted in priority before injection to the first electrical connection layer.

3. A light-emitting diode chip, comprising:
a light-emitting epitaxial laminated layer including a first-type semiconductor layer, a second-type semiconductor layer and an active layer between them, which has two surfaces opposite to each other, wherein, the second surface is the light-emitting surface;
a first electrical connection layer over the first surface of the light-emitting epitaxial laminated layer, which is composed of first geometric pattern arrays;
a second electrical connection layer over the second surface of the light-emitting epitaxial laminated layer, which is composed of second geometric pattern arrays; and
a transparent current spreading layer over the surface of the second electrical connection layer;
wherein, when external power is connected, the horizontal resistance of current passing through the transparent current spreading layer is less than that passing through the second electrical connection layer;
wherein the light-emitting diode chip is fabricated with a method comprising:
1) providing the light-emitting epitaxial laminated layer, comprising the first-type semiconductor layer, the second-type semiconductor layer and the active layer between them, which has two surfaces opposite to each other, wherein, the second surface is the light-emitting surface;
2) fabricating the first electrical connection layer over the first surface of the light-emitting epitaxial laminated layer, which is composed of the first geometric pattern arrays;
3) fabricating the second electrical connection layer over the second surface of the light-emitting epitaxial laminated layer, which is composed of the second geometric pattern arrays;
4) fabricating the transparent current spreading layer over the surface of the second electrical connection layer; when the external power is connected, the horizontal resistance of current passing through the transparent current spreading layer is less than that passing through the first electrical connection layer;
wherein step 3) comprises evaporating the second electrical connection layer over the second surface of the light-emitting epitaxial laminated layer; evaporating the second dielectric material layer over the surface; etching the second electrical connection layer region to expose the second electrical connection layer; and flattening the surface of the second connection layer through chemical mechanical polishing.

4. The light-emitting diode chip of claim 3 , wherein the light-emitting epitaxial laminated layer comprises an AlGaInP-based material.

5. The light-emitting diode chip of claim 3 , further comprising a top electrode over the second electrical connection layer, in which, when current is injected to the top electrode and conducted to the transparent current spreading layer, it is horizontally conducted in priority before injection to the second electrical connection layer.

6. The light-emitting diode chip of claim 5 , wherein the first geometric pattern array and the second geometric pattern array are alternatively arranged.

7. The light-emitting diode chip of claim 5 , wherein average surface roughness of the second electrical connection layer Ra is 1 nm or below.

8. The light-emitting diode chip of claim 5 , wherein the second electrical connection layer is AuGe, AuGeNi, or TiAu alloy.

9. The light-emitting diode chip of claim 5 , wherein the first geometric pattern array is not connected due to isolation by the first dielectric material, and the second geometric pattern array is not connected due to isolation by the second dielectric material.

10. The light-emitting diode chip of claim 9 , wherein the second dielectric material is composed of anti-reflection single-layer or multi-layer materials, which increases radiation light source penetration of the active layer and reduces optical loss.

11. The light-emitting diode chip of claim 9 , wherein the first dielectric material is composed of single-layer or multi-layer materials, which reflects radiation light source of the active layer and reduces optical loss.

12. The light-emitting diode chip of claim 9 , wherein the second geometric pattern array area equals to or is less than 1/10 of the light-emitting area of the light-emitting epitaxial laminated layer.

13. A light-emitting system comprising a plurality of light-emitting diodes, each light-emitting diode including:
a light-emitting epitaxial laminated layer comprising a first-type semiconductor layer, a second-type semiconductor layer and an active layer between them, which has two surfaces opposite to each other, wherein, the second surface is the light-emitting surface;
a first electrical connection layer over the first surface of the light-emitting epitaxial laminated layer, which is composed of first geometric pattern arrays;
a second electrical connection layer over the second surface of the light-emitting epitaxial laminated layer, which is composed of second geometric pattern arrays; and
a transparent current spreading layer over the surface of the second electrical connection layer;
wherein, when external power is connected, the horizontal resistance of current passing through the transparent current spreading layer is less than that passing through the second electrical connection layer;
wherein the each light-emitting diode is fabricated with a method comprising:
1) providing the light-emitting epitaxial laminated layer, comprising the first-type semiconductor layer, the second-type semiconductor layer and the active layer between them, which has two surfaces opposite to each other, wherein, the second surface is the light-emitting surface;
2) fabricating the first electrical connection layer over the first surface of the light-emitting epitaxial laminated layer, which is composed of the first geometric pattern arrays;
3) fabricating the second electrical connection layer over the sec

Assignees

• Xiamen Sanan Optoelectronics Technology Co Ltd

Inventors

• Yang shu-fan
• Wu Chun-Yi
• Wu Chaoyu
• Wang Duxiang

Classifications

• H01L2933/0016

  Electricity · mapped topic

• H01L51/445 Primary

  Electricity · mapped topic

• H01L33/382

  Electricity · mapped topic

• H01L33/14

  Electricity · mapped topic

• H01L33/42

  Electricity · mapped topic