Tunneling field effect transistor

Patent metadata

Field	Value
Publication number	US-10340369-B2
Application number	US-201715703484-A
Country	US
Kind code	B2
Filing date	Sep 13, 2017
Priority date	Oct 1, 2014
Publication date	Jul 2, 2019
Grant date	Jul 2, 2019

Abstract

A tunneling field effect transistor device disclosed herein includes a substrate, a body comprised of a first semiconductor material being doped with a first type of dopant material positioned above the substrate, and a second semiconductor material positioned above at least a portion of the gate region and above the source region. The first semiconductor material is part of the drain region, and the second semiconductor material defines the channel region. The device also includes a third semiconductor material positioned above the second semiconductor material and above at least a portion of the gate region and above the source region. The third semiconductor material is part of the source region, and is doped with a second type of dopant material that is opposite to the first type of dopant material. A gate structure is positioned above the first, second and third semiconductor materials in the gate region.

First claim

What is claimed:

1. A tunneling field effect transistor device comprising a drain region, a source region and a gate region, the device comprising:
a semiconductor substrate;
a body comprised of a first semiconductor material being doped with a first type of dopant material positioned above said substrate, said body having an axis that is oriented substantially perpendicular to an upper surface of said substrate, said body having two side surfaces and an upper surface, said body extending a full length of said drain region, said gate region and said source region, wherein said first semiconductor material is part of said drain region;
a second semiconductor material positioned above at least a portion of said gate region and above said source region, wherein said second semiconductor material defines said channel region;
a third semiconductor material positioned above said second semiconductor material and above at least a portion of said gate region and above said source region, said third semiconductor material being doped with a second type of dopant material that is opposite to said first type of dopant material, wherein said third semiconductor material is part of said source region; and
a gate structure positioned above said first, second and third semiconductor materials in said gate region, wherein said gate structure includes a gate insulation layer and said third semiconductor material has an uppermost surface having a height greater than a height of an uppermost surface of said gate insulation layer.

2. The device of claim 1 , wherein said first semiconductor material, said second semiconductor material and said third semiconductor material are each comprised of a group III-V compound semiconductor material or a group IV material.

3. The device of claim 1 , wherein said first semiconductor material, said second semiconductor material and said third semiconductor material are each made of different semiconductor materials.

4. The device of claim 1 , wherein said second semiconductor material extends across substantially the entire gate region in a direction that corresponds to a channel length direction of said device.

5. The device of claim 1 , wherein said third semiconductor material extends only partially across said gate region in a direction that corresponds to a channel length direction of said device.

6. The device of claim 1 , wherein said second semiconductor material is an updoped material.

7. The device of claim 1 , wherein said gate structure is positioned around said upper surface of said body and at least a portion of said two side surfaces of said body.

8. The device of claim 1 , wherein said third semiconductor material has a dopant concentration of said second dopant material that falls within a range of 5×10 18 -8×10 19 ion/cm 3 and said first semiconductor material has a dopant concentration of said first dopant material that falls within a range of 5×10 19 -1×10 21 ion/cm 3 .

9. The device of claim 1 , further comprising a band-offset buffer semiconductor material positioned between said body and said substrate.

10. The device of claim 1 , wherein said third semiconductor material has a first thickness in said gate region, and a second thickness greater than said first thickness in said source region.

11. A tunneling field effect transistor device, comprising:
a semiconductor substrate;
a drain region comprising a first semiconductor material doped with a first type of dopant material positioned above said substrate, said drain region having an axis that is oriented substantially perpendicular to an upper surface of said substrate, said drain region having two side surfaces and an upper surface;
a channel region comprising a second semiconductor material positioned above at least a portion of said source region on said two side surfaces and said upper surface;
a source region comprising a third semiconductor material positioned above at least a portion of said second semiconductor material above said two side surfaces and said upper surface, said third semiconductor material being doped with a second type of dopant material that is opposite to said first type of dopant material; and
a gate structure positioned above said first, second and third semiconductor materials in a gate region.

12. The device of claim 11 , wherein said first semiconductor material, said second semiconductor material and said third semiconductor material are each comprised of a group III-V compound semiconductor material or a group IV material.

13. The device of claim 11 , wherein said first semiconductor material, said second semiconductor material and said third semiconductor material are each made of different semiconductor materials.

14. The device of claim 11 , wherein said second semiconductor material extends across substantially the entire gate region in a direction that corresponds to a channel length direction of said device.

15. The device of claim 11 , wherein said third semiconductor material extends only partially across said gate region in a direction that corresponds to a channel length direction of said device.

16. The device of claim 11 , wherein said second semiconductor material is an updoped material.

17. The device of claim 11 , further comprising a band-offset buffer semiconductor material positioned between said body and said substrate.

18. The device of claim 11 , wherein said gate structure includes a gate insulation layer and said third semiconductor material has an uppermost surface having a height greater than a height of an uppermost surface of said gate insulation layer.

19. The device of claim 11 , wherein said third semiconductor material has a first thickness in said gate region, and a second thickness greater than said first thickness outside said gate region.

20. A tunneling field effect transistor device comprising a drain region, a source region and a gate region, the device comprising:
a semiconductor substrate;
a body comprised of a first semiconductor material being doped with a first type of dopant material positioned above said substrate, said body having an axis that is oriented substantially perpendicular to an upper surface of said substrate, said body having two side surfaces and an upper surface, said body extending a full length of said drain region, said gate region and said source region, wherein said first semiconductor material is part of said drain region;
a band-offset buffer semiconductor material positioned between said body and said substrate;
a second semiconductor material positioned above at least a portion of said gate region and above said source region, wherein said second semiconductor material defines said channel region;
a third semiconductor material positioned above said second semiconductor material and above at least a portion of said gate region and above said source region, said third semiconductor material being doped with a second type of dopant material that is opposite to said first type of dopant material, wherein said third semiconductor material is part of said source region; and
a gate structure positioned above said first, second and third semiconductor materials in said gate region.

Assignees

• Globalfoundries Inc

Inventors

• Pawlak Bartlomiej Jan

Classifications

• H01L29/0834

  Electricity · mapped topic

• H01L29/267

  Electricity · mapped topic

• H01L29/083

  Electricity · mapped topic

• H01L21/823418

  Electricity · mapped topic

• H01L29/7848

  Electricity · mapped topic