Semiconductor device including an LDMOS transistor and a resurf structure

Patent metadata

Field	Value
Publication number	US-10340334-B2
Application number	US-201815986942-A
Country	US
Kind code	B2
Filing date	May 23, 2018
Priority date	Jun 24, 2016
Publication date	Jul 2, 2019
Grant date	Jul 2, 2019

Abstract

In an embodiment, a semiconductor device includes a semiconductor substrate having a bulk resistivity ρ≥100 Ohm.cm, a front surface and a rear surface. An LDMOS transistor is arranged in the semiconductor substrate. A RESURF structure including a doped buried layer is arranged in the semiconductor substrate. The LDMOS transistor includes a body contact region doped with a first conductivity type, and a source region disposed in the body contact region and doped with a second conductivity type opposite the first conductivity type. The source region includes a first well and a second well of the same second conductivity type. The first well is more highly doped than the second well. The first well extends from inside the body contact region to outside of a lateral extent of the body contact region in a direction towards a source side of a gate of the LDMOS transistor.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate having a bulk resistivity ρ≥100 Ohm.cm, a front surface and a rear surface;
an LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistor in the semiconductor substrate; and
a RESURF (REduced SURface Field structure) structure comprising a doped buried layer arranged in the semiconductor substrate,
wherein the LDMOS transistor comprises a body contact region doped with a first conductivity type, and a source region disposed in the body contact region and doped with a second conductivity type opposite the first conductivity type,
wherein the source region comprises a first well and a second well of the same second conductivity type,
wherein the first well is more highly doped than the second well,
wherein the first well extends from inside the body contact region to outside of a lateral extent of the body contact region in a direction towards a source side of a gate of the LDMOS transistor.

2. The semiconductor device of claim 1 , wherein the doped buried layer is spaced at a distance from the front surface and the rear surface, and coupled with at least one of a channel region and the body contact region of the LDMOS transistor, and wherein the RESURF structure further comprises:
a lightly doped region extending from the gate towards a drain region of the LDMOS transistor; and
at least one field plate.

3. The semiconductor device of claim 1 , wherein the doped buried layer extends continuously throughout a lateral area of the semiconductor substrate.

4. The semiconductor device of claim 1 , wherein the doped buried layer extends continuously under a drain region, the source region and the gate of the LDMOS transistor.

5. The semiconductor device of claim 1 , wherein the second well extends further into the substrate than the first well by a distance less than that of a channel region of the LDMOS transistor and is positioned entirely within the body contact region.

6. The semiconductor device of claim 1 , further comprising a first dielectric layer on the front surface of the substrate having an opening above a drain region of the LDMOS transistor in which a drain metal contact is formed, and an opening over the source region of the LDMOS transistor in which a source metal contact is formed.

7. The semiconductor device of claim 6 , wherein the first dielectric layer covers the gate of the LDMOS transistor and extends between a source-sided edge of the gate and the source metal contact and between a drain-sided edge of the gate and the drain metal contact.

8. The semiconductor device of claim 6 , further comprising a field plate positioned on the first dielectric layer above the gate and extending on the first dielectric layer in a direction of the drain metal contact.

9. The semiconductor device of claim 8 , further comprising a second dielectric layer that extends over the source metal contact, over a portion of the first dielectric layer positioned between the source metal contact and the field plate, over the gate, over the field plate, over a portion of the first dielectric layer extending between the field plate and the drain metal contact, and over the drain metal contact.

10. The semiconductor device of claim 9 , wherein the second dielectric layer comprises a first sublayer of silicon oxynitride and a second sublayer of silicon dioxide on the first sublayer.

11. The semiconductor device of claim 9 , further comprising a gate shield arranged on the second dielectric layer above the gate and extending in a direction of the source region.

12. The semiconductor device of claim 11 , wherein the gate shield is conformally deposited on the second dielectric layer and partially overlaps a gate-sided end of the field plate.

13. The semiconductor device of claim 1 , further comprising a conductive via extending from the front surface to the rear surface of the substrate, wherein the conductive via includes a first conductive portion adjacent the rear surface which fills a lower portion of the conductive via and a second conductive portion arranged on the first portion which lines side walls of the via and surrounds a gap, wherein the gap is sealed at the top to form a void within an upper portion of the conductive via.

14. The semiconductor device of claim 13 , wherein the second conductive portion extends over the front surface of the substrate and is arranged directly on and electrically coupled with a conductive layer coupled to a source metal contact at a position adjacent the source region of the LDMOS transistor.

15. The semiconductor device of claim 1 , further comprising a conductive via extending through the semiconductor substrate from the front surface to the rear surface and through a dielectric layer formed on the front surface, wherein the conductive via electrically connects a conductive layer arranged on the rear surface to a metallic layer arranged on the dielectric layer, and wherein the metallic layer is electrically connected to the source region by a conductive via which extends through the dielectric layer to a source metal contact.

16. The semiconductor device of claim 1 , further comprising a conductive via extending through the semiconductor substrate from the front surface to the rear surface, including through the body contact region.

17. A high frequency amplifying circuit, comprising:
an RF power amplifying circuit formed in a semiconductor substrate,
wherein the semiconductor substrate has a bulk resistivity ρ≥100 Ohm.cm, a front surface and a rear surface;
wherein the RF power amplifying circuit comprises an LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistor in the semiconductor substrate, and a RESURF (REduced SURface Field structure) structure comprising a doped buried layer arranged in the semiconductor substrate,
wherein the LDMOS transistor comprises a body contact region doped with a first conductivity type, and a source region disposed in the body contact region and doped with a second conductivity type opposite the first conductivity type,
wherein the source region comprises a first well and a second well of the same second conductivity type,
wherein the first well is more highly doped than the second well,
wherein the first well extends from inside the body contact region to outside of a lateral extent of the body contact region in a direction towards a source side of a gate of the LDMOS transistor.

18. The high frequency amplifying circuit of claim 17 , wherein the RF power amplifying circuit is configured for cellular communications in an operating frequency range of 700 MHz to 3.6 GHz.

19. The high frequency amplifying circuit of claim 17 , wherein the RF power amplifying circuit is configured for power conversion in cellular communication networks.

20. The high frequency amplifying circuit of claim 17 , wherein the RF power amplifying circuit is a Doherty amplifying circuit.

Assignees

• Infineon Technologies Ag

Inventors

• Birner Albert
• Brech Helmut
• Zigldrum Matthias
• Braun Michaela
• Eckl Christian

Classifications

• H10W20/216

  characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes · CPC title

• H03F1/0288

  using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title

• H03F3/193

  with field-effect devices (H03F3/195 takes precedence) · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title