Contact resistance reduction technique

Patent metadata

Field	Value
Publication number	US-10340269-B2
Application number	US-201715397203-A
Country	US
Kind code	B2
Filing date	Jan 3, 2017
Priority date	Oct 15, 2014
Publication date	Jul 2, 2019
Grant date	Jul 2, 2019

Abstract

An embodiment is a method of manufacturing a semiconductor device, the method including forming a first gate over a substrate, forming a recess in the substrate adjacent the first gate, epitaxially forming a strained material stack in the recess, the strained material stack comprising at least three layers, each of the at least three layers comprising a dopant. The method further includes co-implanting the strained material stack with dopants comprising boron, germanium, indium, tin, or a combination thereof, forming a metal layer on the strained material stack, and annealing the metal layer and the strained material stack forming a metal-silicide layer.

First claim

What is claimed is:

1. A device comprising:
a fin extending from a substrate;
a gate structure on a top surface and sidewalls of the fin;
a strained material stack on the fin adjacent the gate structure, the strained material stack comprising:
a first boron-doped (B-doped) silicon-germanium (SiGeB) layer on the fin;
a second SiGeB layer on the first SiGeB layer, the second SiGeB layer having a higher concentration of Ge than the first SiGeB layer;
a B-doped germanium-tin (GeSnB) layer on the second SiGeB layer; and
a third SiGeB layer on the GeSnB layer;

a metal-silicide layer on the third SiGeB layer; and
a metal contact on the metal-silicide layer.

2. The device of claim 1 , wherein the metal-silicide layer comprises nickel, titanium, or a combination thereof.

3. The device of claim 1 , further comprising gate spacers on opposite sides of the gate structure, wherein the gate structure comprises:
a gate dielectric contacting the top surface of the fin and sidewalls of the gate spacers
a gate electrode over the gate dielectric.

4. The device of claim 1 , wherein the metal-silicide layer has a specific contact resistivity to the third SiGeB layer of about 1.6×10 −9 Ohms-cm 2 .

5. The device of claim 1 , wherein the GeSnB layer is thinner than the first SiGeB layer and the second SiGeB layer.

6. A device comprising:
a fin extending from a substrate;
a gate structure on a top surface and sidewalls of the fin;
a strained material stack on the fin adjacent the gate structure, the strained material stack comprising:
a first boron-doped (B-doped) silicon-germanium (SiGeB) layer on the fin, the first SiGeB layer having a first Ge concentration;
a second SiGeB layer on the first SiGeB layer;
a tin-doped (Sn-doped) germanium-containing layer on the second SiGeB layer, the germanium-containing layer further doped with B, the germanium-containing layer having a second Ge concentration higher than the first Ge concentration; and
a third SiGeB layer on the germanium-containing layer;

a metal-silicide layer on the third SiGeB layer; and
a metal contact on the metal-silicide layer.

7. The device of claim 6 , wherein the first Ge concentration of the first SiGeB layer is from about 15% to about 30%.

8. The device of claim 6 , wherein the second Ge concentration of the germanium-containing layer is from about 50% to about 95%.

9. The device of claim 6 , wherein the second SiGeB layer has a graded Ge concentration.

10. The device of claim 9 , wherein the second SiGeB layer has a bottom proximate the first SiGeB layer and a top proximate the germanium-containing layer, the graded Ge concentration increasing from the first Ge concentration at the bottom of the second SiGeB layer to the second Ge concentration at the top of the second SiGeB layer.

11. The device of claim 9 , wherein the third SiGeB layer has a third Ge concentration from about 15% to about 50%.

12. The device of claim 6 , wherein the first SiGeB layer has a thickness from about 10 nm to about 30 nm.

13. The device of claim 6 , wherein the second SiGeB layer has a thickness from about 10 nm to about 30 nm.

14. The device of claim 6 , wherein the germanium-containing layer has a thickness from about 1 nm to about 10 nm.

15. The device of claim 6 , wherein the third SiGeB layer has a thickness from about 2 nm to about 10 nm.

16. A device comprising:
a plurality of fins extending from a substrate;
a gate structure over the plurality of fins;
a plurality of strained material stacks adjacent the gate structure, each of the strained material stacks comprising a germanium-containing layer and a plurality of boron-doped (B-doped) silicon-germanium (SiGeB) layers, the germanium-containing layer interposed between the plurality of SiGeB layers, the germanium-containing layer implanted with a first dopant and a second dopant different from the first dopant;
metal-silicide layers on the strained material stacks; and
a metal contact contacting the metal-silicide layers.

17. The device of claim 16 , wherein the first dopant is Sn.

18. The device of claim 17 , wherein the germanium-containing layer has a Sn concentration from about 0.1% to about 9%.

19. The device of claim 17 , wherein the second dopant is B.

20. The device of claim 19 , wherein the germanium-containing layer has a B concentration from about 1E20 atoms/cm 3 to about 8E20 atoms/cm 3 .

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsai Chun Hsiung
• Chen Ming-Te

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title