Through substrate vias with improved connections

Patent metadata

Field	Value
Publication number	US-10340205-B2
Application number	US-201715645928-A
Country	US
Kind code	B2
Filing date	Jul 10, 2017
Priority date	Apr 28, 2010
Publication date	Jul 2, 2019
Grant date	Jul 2, 2019

Abstract

A device includes a substrate, and a plurality of dielectric layers over the substrate. A plurality of metallization layers is formed in the plurality of dielectric layers, wherein at least one of the plurality of metallization layers comprises a metal pad. A through-substrate via (TSV) extends from the top level of the plurality of the dielectric layers to a bottom surface of the substrate. A deep conductive via extends from the top level of the plurality of dielectric layers to land on the metal pad. A metal line is formed over the top level of the plurality of dielectric layers and interconnecting the TSV and the deep conductive via.

First claim

What is claimed is:

1. A device comprising:
a substrate;
an interconnect structure over the substrate, the interconnect structure comprising:
a plurality of low-k dielectric layers;
a plurality of metallization layers in the plurality of low-k dielectric layers and comprising metal pads, wherein the metal pads comprises copper; and
a dielectric layer over the plurality of metallization layers, wherein a k value of the dielectric layer is higher than k values of the plurality of low-k dielectric layers;

a through-substrate via (TSV) extending from a top surface of the dielectric layer to a bottom surface of the substrate;
a first deep conductive via extending from the top surface of the dielectric layer and terminating on a first metal pad in a first one of the plurality of metallization layers;
a second deep conductive via extending from the top surface of the dielectric layer and terminating on a second metal pad in a second one of the plurality of metallization layers different from the first one; and
a metal line over the dielectric layer and electrically coupling the TSV to the first and the second deep conductive vias.

2. The device of claim 1 , wherein the dielectric layer is formed of a non-low-k dielectric material.

3. The device of claim 1 , wherein the TSV and the first and the second deep conductive vias form a continuous region with no diffusion barrier layer separating the TSV from the first and the second deep conductive vias.

4. The device of claim 1 , wherein:
the first deep conductive via has a first width when viewed from cross section and a first height extending from topmost surface to bottommost surface of the first conductive via;
the second deep conductive via has a second width when viewed from cross section and a second height extending from topmost surface to bottommost surface of the second conductive via;
the TSV has a third width when viewed from cross section and a third height extending from topmost surface to bottommost surface of the TSV;
the third width is greater than the second width and the first width and the third height is greater than the second height and the first height; and
the second width is greater than the first width and the second height is greater than the first height.

5. The device of claim 1 , further comprising:
a passivation layer over the metal line; and
a metal bump over the passivation layer, the metal bump disposed outside a lateral extent of the metal line.

6. The device of claim 1 , further comprising:
an interlayer dielectric (ILD) disposed over the substrate and under the plurality of metallization layers, the bottommost surface of the first metal pad being above the topmost surface of the ILD.

7. The device of claim 1 , further comprising a third deep conductive via extending from the top surface of the dielectric layer to land on a third metal pad in a third one of the plurality of metallization layers different from the first one and the second one.

8. The device of claim 1 , wherein the first metal pad is positioned in the bottom level of the plurality of metallization layers.

9. A device comprising:
a substrate;
an interconnect structure on the substrate, the interconnect structure including stacked metallization layers;
a dielectric layer over the stacked metallization layers;
a first conductive via extending from a top surface of the dielectric layer to at least partially into the substrate;
a second conductive via extending from the top surface of the dielectric layer through at least one first metallization layer of the stacked metallization layers and extending to a metal pad of the interconnect structure, the metal pad being formed in a second metallization layer of the stacked metallization layer; and
a single continuous metal feature filling the first conductive via, extending over the top surface of the dielectric layer, and filling the conductive second via.

10. The device of claim 9 , further comprising a third conductive via extending from the top surface of the dielectric layer to a second metal pad of the interconnect structure, the second metal pad being on a different level of the interconnect structure relative to the metal pad.

11. The device of claim 10 , wherein the single continuous metal feature fills the third via.

12. The device of claim 9 , further comprising an interlayer dielectric (ILD) disposed over the substrate and under the interconnect structure, the bottommost surface of the metal pad being above the topmost surface of the ILD.

13. The device of claim 9 , wherein the substrate is substantially free from integrated circuit devices.

14. The device of claim 9 , further comprising a barrier layer encircling the second conductive via.

15. The device of claim 9 , further comprising a passivation layer over the single continuous metal feature; and
a metal bump over the passivation layer, the metal bump disposed outside a lateral extent of the metal line.

16. A device comprising:
a substrate;
an interconnect structure over the substrate, the interconnect structure including a stack of metallization layers respectively embedded in respective dielectric layers;
a through-substrate via (TSV) extending from the top level of the interconnect structure to a bottom surface of the substrate;
a deep conductive via extending from the top level of the interconnect structure through at least one first dielectric layer of the interconnect structure and contacting a metal pad embedded in a second dielectric layer of the interconnect structure, the second dielectric layer being closer to the substrate than the at least one first dielectric layer;
a barrier layer encircling the deep conductive via;
a metal line over the top level of the interconnect structure extending continuously from the TSV to the deep conductive via; and
a passivation layer over the metal line.

17. The device of claim 16 , further comprising a second deep conductive via extending from the top level of the interconnect structure and contacting a second metal pad in the interconnect structure.

18. The device of claim 17 , wherein the interconnect structure includes a stack of metallization layers and wherein the metal pad is in a first one of the stack of metallization layers and the second metal pad is in a second one, different than the first one, of the stack of metallization layers.

19. The device of claim 17 , further comprising an interlayer dielectric (ILD) disposed over the substrate and under the interconnect structure, the bottommost surface of the metal pad and the second metal pad being above the topmost surface of the ILD.

20. The device of claim 16 , further comprising a metal bump over the passivation layer, the metal bump disposed outside a lateral extent of the metal line.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Jing-Cheng
• Yang Ku-Feng

Classifications

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/248

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/244

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title